Mobile charges in MoS2/high-k oxide transistors: from abnormal instabilities to memory-like dynamics
Shaokai Zhou, Haihui Cai, Yehao Wu, Yufeng Min, Renchen Yuan, Yezhu Lv, Jianming Huang, Yuanyuan Shi, Yury Yuryevich Illarionov
TL;DR
This work addresses the stability and memory potential of MoS$_2$ FETs with high-k gate oxides by conducting a temperature-resolved, cross-material study of gate hysteresis. It combines systematic hysteresis_mappings with a compact mobile-charge drift model to explain how oxygen-vacancy migration in HfO$_2$ can induce memory-like CCW hysteresis and NDR, while Al$_2$O$_3$ shows superior high-temperature stability due to higher activation barriers. The findings reveal an insulator-selection paradigm: Al$_2$O$_3$ optimizes logic stability, whereas HfO$_2$ can be leveraged as an active memory layer by exploiting abnormal high-temperature instabilities. The model and measurements together provide design rules for controlling memory versus stability in 2D MoS$_2$ devices, enabling targeted applications in high-temperature electronics and novel memory concepts.
Abstract
MoS$_2$ field-effect transistors (FETs) with high-\textit{k} oxides currently lag behind silicon standards in bias and temperature stability due to ubiquitous border oxide traps that cause clockwise (CW) hysteresis in gate transfer characteristics. While suppressing this effect is typically mandatory for logic FETs, here we explore an alternative strategy where the initial CW hysteresis can be dynamically overcome by stronger counterclockwise (CCW) hysteresis towards memory-like dynamics. We systematically compare hysteresis in similar back-gated MoS$_2$/HfO$_2$ and MoS$_2$/Al$_2$O$_3$ FETs up to 275\textdegree C. At room temperature, both devices initially show sizable CW hysteresis. However, at 175\textdegree C MoS$_2$/HfO$_2$ FETs exhibit dominant CCW dynamics coupled with self-doping and negative differential resistance (NDR) effects. Our compact model suggests that this behavior is caused by the drift of mobile oxygen vacancies (\textit{V}\({}_{\mathrm{O}}^{+}\) or \textit{V}\({}_{\mathrm{O}}^{2+}\)) within HfO$_2$ which also causes negative $V_{\mathrm{th}}$ shift under a constant positive bias stress. This alternative mechanism effectively overrides the initial CW hysteresis and enables intrinsic memory functionality that can be enhanced by using narrower gate bias sweep ranges. In contrast, the MoS$_2$/Al$_2$O$_3$ FETs display only minor CCW dynamics even at 275\textdegree C due to higher drift activation energies for the same vacancies, thereby maintaining superior stability. Our results reveal an insulators selection paradigm: Al$_2$O$_3$ layers are better suited to suppress detrimental negative $V_{\mathrm{th}}$ shifts in MoS$_2$ logic FETs at high temperatures, whereas their HfO$_2$ counterparts can serve as active memory layers that would exploit these abnormal instabilities.
