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Mobile charges in MoS2/high-k oxide transistors: from abnormal instabilities to memory-like dynamics

Shaokai Zhou, Haihui Cai, Yehao Wu, Yufeng Min, Renchen Yuan, Yezhu Lv, Jianming Huang, Yuanyuan Shi, Yury Yuryevich Illarionov

TL;DR

This work addresses the stability and memory potential of MoS$_2$ FETs with high-k gate oxides by conducting a temperature-resolved, cross-material study of gate hysteresis. It combines systematic hysteresis_mappings with a compact mobile-charge drift model to explain how oxygen-vacancy migration in HfO$_2$ can induce memory-like CCW hysteresis and NDR, while Al$_2$O$_3$ shows superior high-temperature stability due to higher activation barriers. The findings reveal an insulator-selection paradigm: Al$_2$O$_3$ optimizes logic stability, whereas HfO$_2$ can be leveraged as an active memory layer by exploiting abnormal high-temperature instabilities. The model and measurements together provide design rules for controlling memory versus stability in 2D MoS$_2$ devices, enabling targeted applications in high-temperature electronics and novel memory concepts.

Abstract

MoS$_2$ field-effect transistors (FETs) with high-\textit{k} oxides currently lag behind silicon standards in bias and temperature stability due to ubiquitous border oxide traps that cause clockwise (CW) hysteresis in gate transfer characteristics. While suppressing this effect is typically mandatory for logic FETs, here we explore an alternative strategy where the initial CW hysteresis can be dynamically overcome by stronger counterclockwise (CCW) hysteresis towards memory-like dynamics. We systematically compare hysteresis in similar back-gated MoS$_2$/HfO$_2$ and MoS$_2$/Al$_2$O$_3$ FETs up to 275\textdegree C. At room temperature, both devices initially show sizable CW hysteresis. However, at 175\textdegree C MoS$_2$/HfO$_2$ FETs exhibit dominant CCW dynamics coupled with self-doping and negative differential resistance (NDR) effects. Our compact model suggests that this behavior is caused by the drift of mobile oxygen vacancies (\textit{V}\({}_{\mathrm{O}}^{+}\) or \textit{V}\({}_{\mathrm{O}}^{2+}\)) within HfO$_2$ which also causes negative $V_{\mathrm{th}}$ shift under a constant positive bias stress. This alternative mechanism effectively overrides the initial CW hysteresis and enables intrinsic memory functionality that can be enhanced by using narrower gate bias sweep ranges. In contrast, the MoS$_2$/Al$_2$O$_3$ FETs display only minor CCW dynamics even at 275\textdegree C due to higher drift activation energies for the same vacancies, thereby maintaining superior stability. Our results reveal an insulators selection paradigm: Al$_2$O$_3$ layers are better suited to suppress detrimental negative $V_{\mathrm{th}}$ shifts in MoS$_2$ logic FETs at high temperatures, whereas their HfO$_2$ counterparts can serve as active memory layers that would exploit these abnormal instabilities.

Mobile charges in MoS2/high-k oxide transistors: from abnormal instabilities to memory-like dynamics

TL;DR

This work addresses the stability and memory potential of MoS FETs with high-k gate oxides by conducting a temperature-resolved, cross-material study of gate hysteresis. It combines systematic hysteresis_mappings with a compact mobile-charge drift model to explain how oxygen-vacancy migration in HfO can induce memory-like CCW hysteresis and NDR, while AlO shows superior high-temperature stability due to higher activation barriers. The findings reveal an insulator-selection paradigm: AlO optimizes logic stability, whereas HfO can be leveraged as an active memory layer by exploiting abnormal high-temperature instabilities. The model and measurements together provide design rules for controlling memory versus stability in 2D MoS devices, enabling targeted applications in high-temperature electronics and novel memory concepts.

Abstract

MoS field-effect transistors (FETs) with high-\textit{k} oxides currently lag behind silicon standards in bias and temperature stability due to ubiquitous border oxide traps that cause clockwise (CW) hysteresis in gate transfer characteristics. While suppressing this effect is typically mandatory for logic FETs, here we explore an alternative strategy where the initial CW hysteresis can be dynamically overcome by stronger counterclockwise (CCW) hysteresis towards memory-like dynamics. We systematically compare hysteresis in similar back-gated MoS/HfO and MoS/AlO FETs up to 275\textdegree C. At room temperature, both devices initially show sizable CW hysteresis. However, at 175\textdegree C MoS/HfO FETs exhibit dominant CCW dynamics coupled with self-doping and negative differential resistance (NDR) effects. Our compact model suggests that this behavior is caused by the drift of mobile oxygen vacancies (\textit{V} or \textit{V}) within HfO which also causes negative shift under a constant positive bias stress. This alternative mechanism effectively overrides the initial CW hysteresis and enables intrinsic memory functionality that can be enhanced by using narrower gate bias sweep ranges. In contrast, the MoS/AlO FETs display only minor CCW dynamics even at 275\textdegree C due to higher drift activation energies for the same vacancies, thereby maintaining superior stability. Our results reveal an insulators selection paradigm: AlO layers are better suited to suppress detrimental negative shifts in MoS logic FETs at high temperatures, whereas their HfO counterparts can serve as active memory layers that would exploit these abnormal instabilities.
Paper Structure (22 sections, 13 equations, 17 figures)

This paper contains 22 sections, 13 equations, 17 figures.

Figures (17)

  • Figure 1: (a) Schematic layout of our back-gated MoS$_2$/HfO$_2$ and MoS$_2$/Al$_2$O$_3$ FETs fabricated using the same process. The channel is made of CVD-grown MoS$_2$ films taken from the same batch. (b) Optical image of four devices inside the array containing tens of FETs. (c) $I_{\mathrm{D}}$-$V_{\mathrm{G}}$ characteristics of MoS$_2$ FETs with Al$_2$O$_3$ (left) and HfO$_2$ (right) measured at different $V_{\mathrm{D}}$. The insets show the corresponding $I_{\mathrm{D}}$-$V_{\mathrm{D}}$ curves. (d) Schematics of the subsequent $V_{\mathrm{G}}$ sweeps with increased $t_{\mathrm{sw}}$ used in our hysteresis measurements. In some measurements maximum $t_{\mathrm{sw}}$ that we have reached was above 10$\,$ks. (e) Schematics of our universal mapping method LV25M which suggests scanning the $I_{\mathrm{D}}$ values to obtain minimum (lower UHF) and maximum (upper UHF) from the extracted family of $\Delta V_{\mathrm{H}}$(1/$t_{\mathrm{sw}}$) curves.
  • Figure 2: (a) Double sweep $I_{\mathrm{D}}$-$V_{\mathrm{G}}$ characteristics of 5 MoS$_2$ FETs with Al$_2$O$_3$ (left) and HfO$_2$ (right) with different $L$ and $W$ measured using the slowest achieved sweeps at 25° C. A purely CW hysteresis is present for all devices. (b) The corresponding $\Delta V_{\mathrm{H}}$ vs. $1/t_{\text{sw}}$ dependences showing that while there is some device-to-device variability for both types of devices, in overall the CW hysteresis is smaller for the devices with Al$_2$O$_3$. (c) Double sweep $I_{\mathrm{D}}$-$V_{\mathrm{G}}$ characteristics of the representative MoS$_2$ FETs with Al$_2$O$_3$ (left) and HfO$_2$ (right) measured using the slowest $t_{\mathrm{sw}}$ and different $V_{\mathrm{G}}$ sweep ranges. (d) The corresponding $\Delta V_{\mathrm{H}}$ vs. $1/t_{\text{sw}}$ curves confirm that for the MoS$_2$/Al$_2$O$_3$ FETs hysteresis is smaller for all $V_{\mathrm{G}}$ sweep ranges. Remarkably, the results for -6 to 2$\,$V sweep range repeated in three rounds (r1, r2, r3) in the beginning and in the end of experiment (as illustrated by the arrow next to the legend) show perfect reproducibility. (e) Band diagram showing relative energetic alignments between the conduction band edge $E_{\mathrm{C}}$ of the MoS$_2$ n-channel and known fundamental defect bands in HfO$_2$ and Al$_2$O$_3$RZEPA18ILLARIONOV20A. The upper defect band of HfO$_2$ is closer to $E_{\mathrm{C}}$ of MoS$_2$, while the defect band of Al$_2$O$_3$ is situated deeper. This explains smaller CW hysteresis in the latter case, since deeper traps in Al$_2$O$_3$ get activated at slower sweeps.
  • Figure 3: (a) Double sweep $I_{\mathrm{D}}$-$V_{\mathrm{G}}$ characteristics of our MoS$_2$/HfO$_2$ FET measured at $T\,=\,$175° C using 8 subsequent sweeps with $t_{\mathrm{sw}}$ up to 12.1$\,$ks. The hysteresis dynamics changes from the CW/CCW switching at faster sweeps to the purely CCW hysteresis at slower sweeps. (b) The corresponding mapping results which clearly reveal the frequency ranges of both hysteresis dynamics and a distinct maximum of the CCW hysteresis. (c) Linear scale $I_{\mathrm{D}}$-$V_{\mathrm{G}}$ curves corresponding to (a) which show development of the CCW hysteresis, i.e. a weak effect at fast $t_{\mathrm{sw}}$, an NDR behavior at moderate $t_{\mathrm{sw}}$ and an increase of $I_{\mathrm{ON}}$ with localization and decay of the CCW hysteresis at slow $t_{\mathrm{sw}}$. (d,e) The related results measured at $T\,=\,$250° C. The CCW hysteresis maximum is shifted to faster sweeps and thus the CW/CCW switching is observed at slower sweeps. The inset in (e) highlights that NDR is not observed within the $t_{\mathrm{sw}}$ range used since mobile charges are too fast.
  • Figure 4: (a) Double sweep $I_{\mathrm{D}}$-$V_{\mathrm{G}}$ characteristics of the MoS$_2$/HfO$_2$ FET simulated with our compact model using different $t_{\mathrm{sw}}$ and $T\,=\,$175° C. The trends are qualitatively similar to our experimental results shown in Fig.3c. (b) Schematics that illustrate the drift of positive oxygen vacancies in the oxide. At negative $V_{\mathrm{G}}$ they are concentrated at the gate side of HfO$_2$. Then when $V_{\mathrm{G}}$ becomes positive bulk motion towards the MoS$_2$ channel starts if $t_{\mathrm{sw}}$ is slow enough (state 1). However, when approaching MoS$_2$ the charges start feeling the interface effects and thus slowing down (state 1'), before finally getting trapped at the channel side (state 2). The dynamics of the CCW hysteresis and its side features such as the NDR effect and $I_{\mathrm{ON}}$ increase are determined by the relative positions of the points 1, 1' and 2 on the $I_{\mathrm{D}}$-$V_{\mathrm{G}}$ curves that depend on $t_{\mathrm{sw}}$. Also, if the sweep is too slow, the drift of mobile charges back to the gate may start (state 3) when $V_{\mathrm{G}}$ becomes negative during the reverse sweep. (c) The lower UHFs extracted by mapping method from the series of $I_{\mathrm{D}}$-$V_{\mathrm{G}}$ characteristics simulated with different $E_{\mathrm{A}}$. While a maximum of the CCW hysteresis similar to Fig.3b is revealed, a larger $E_{\mathrm{A}}$ shifts it to the slower sweep frequencies and vice versa. The gray box marks typical measurement range.
  • Figure 5: (a) Double sweep $I_{\mathrm{D}}$-$V_{\mathrm{G}}$ characteristics of the MoS$_2$/HfO$_2$ FET measured using slowest achieved $t_{\mathrm{sw}}$ for different $V_{\mathrm{G}}$ sweep ranges and $T\,=\,$175° C. While for -6 to 6$\,$V the CCW hysteresis already starts to localize, for narrower sweep ranges the NDR effect is still present. (b) The lower UHFs obtained for two devices indeed show that for -6 to 6$\,$V the maximum of CCW hysteresis is reached faster which is because with more positive $V_{\mathrm{Gmax}}$ mobile charges need less time to cross $d_{\mathrm{ox}}$ and thus can localize at the channel side of HfO$_2$ earlier. (c) Full set of double sweep $I_{\mathrm{D}}$-$V_{\mathrm{G}}$ curves measured using -6 to 4$\,$V sweep range in a linear scale. Sizable and progressive NDR effect towards slower sweeps is visible. (d) The dependence of NDR magnitude vs. sweep frequency for different sweep ranges. Narrower sweep ranges reveal stronger effect that appears at slower sweeps.
  • ...and 12 more figures