Dual-Mapping Sparse Vector Transmission for Short Packet URLLC

TL;DR

This work targets URLLC by improving short-packet transmission through dual-mapping sparse vector coding (DM-SVC). DM-SVC encodes information with two sparse patterns—block sparsity ($K_b$ blocks of length $L$) and single-element sparsity ($K_s$ elements)—merged as ${\bf s} = \sqrt{\alpha}{\bf s_1} + \sqrt{1-\alpha}{\bf s_2}$ and transmitted after random spreading and IDFT with a CP. A two-stage decoder exploits block-structured sparsity to first identify $K_b$ block indexes and then retrieve $K_s$ single indexes, achieving higher decoding reliability than conventional AMP/MMP-based schemes. Results show DM-SVC outperforms existing SVC-type schemes in block error rate and spectral efficiency, with notable gains such as $\approx$0.5 dB SNR improvement over GSPARC at $\mathrm{BLER}=10^{-5}$ and 12–14% SE gains over SSC for typical modulations, demonstrating practical impact for URLLC systems. The approach offers flexible parameterization (e.g., $L$ and $K_s$) to meet varying reliability and throughput requirements in dynamic short-packet scenarios.

Abstract

Sparse vector coding (SVC) is a promising short-packet transmission method for ultra reliable low latency communication (URLLC) in next generation communication systems. In this paper, a dual-mapping SVC (DM-SVC) based short packet transmission scheme is proposed to further enhance the transmission performance of SVC. The core idea behind the proposed scheme lies in mapping the transmitted information bits onto sparse vectors via block and single-element sparse mappings. The block sparse mapping pattern is able to concentrate the transmit power in a small number of non-zero blocks thus improving the decoding accuracy, while the single-element sparse mapping pattern ensures that the code length does not increase dramatically with the number of transmitted information bits. At the receiver, a two-stage decoding algorithm is proposed to sequentially identify non-zero block indexes and single-element non-zero indexes. Extensive simulation results verify that proposed DM-SVC scheme outperforms the existing SVC schemes in terms of block error rate and spectral efficiency.

Figures (6)

• Figure 1: Diagram of the sparse mapping process of DM-SVC. $b$ bits of information are mapped to a sparse vector of length $N$ containing $K_{\rm b}$ non-zero blocks and $K_{\rm s}$ non-zero elements.
• Figure 2: Comparison of SE of the SSC scheme ZhangXuewan2022 and DM-SVC scheme with different parameters $({{K_{\rm{b}}}},L,{K_{\rm{s}}})$, where $N=138$ and $C=5$.
• Figure 3: BLER vs. power allocation ratio in DM-SVC scheme with $K_{\rm b}=1$, $L=3$, $K_{\rm s}=1$, $N=2100$, $M=96$ and $b=30$.
• Figure 4: BLER of different schemes vs. SNR with $\alpha=0.64$, $K_{\rm b}=1$, $L=3$, $K_{\rm s}=1$, $N=2100$, $M=80$ and $b=30$.
• Figure 5: Impact of $L$ and $K_{\rm s}$ on BLER performance in proposed DM-SVC scheme with $K_{\rm b}=1$ and $M=80$.