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Demonstration of a Field-Effect Three-Terminal Electronic Device with an Electron Mobility Exceeding 40 Million cm^2/(Vs)

T. J. Martz-Oberlander, B. Bulgaru, Z. Berkson-Korenberg, Q. Hawkins, K. W. West, K. W. Baldwin, A. Gupta, L. N. Pfeiffer, G. Gervais

Abstract

We report the fabrication and operation of a source-drain-gate three-terminal field-effect electronic device with an electron mobility exceeding $40\times 10^6$ cm$^2$ / (Vs). Several devices were fabricated, with the highest achieved electron mobility obtained using a symmetrically-doped GaAs/AlGaAs quantum well forming a two-dimensional electron gas (2DEG) with a density of $1.47(1) \times 10^{11}$ cm$^{-2}$ and a pristine, pre-fabrication electron mobility of $44(2) \times 10^6$ cm$^2$/(\text{Vs}). To circumvent the well-known degradation of electron mobility during fabrication, devices were fabricated using a flip-chip technique where all lithographic processing steps were performed on a separate sapphire substrate. This method demonstrates the successful operation of various gate assembly designs on distinct 2DEGs without observable mobility degradation. This advance doubles the previous record for field-effect electronic device mobility and enables access to new regimes of quantum transport and applications that were previously unfathomable due to mobility limitations.

Demonstration of a Field-Effect Three-Terminal Electronic Device with an Electron Mobility Exceeding 40 Million cm^2/(Vs)

Abstract

We report the fabrication and operation of a source-drain-gate three-terminal field-effect electronic device with an electron mobility exceeding cm / (Vs). Several devices were fabricated, with the highest achieved electron mobility obtained using a symmetrically-doped GaAs/AlGaAs quantum well forming a two-dimensional electron gas (2DEG) with a density of cm and a pristine, pre-fabrication electron mobility of cm/(\text{Vs}). To circumvent the well-known degradation of electron mobility during fabrication, devices were fabricated using a flip-chip technique where all lithographic processing steps were performed on a separate sapphire substrate. This method demonstrates the successful operation of various gate assembly designs on distinct 2DEGs without observable mobility degradation. This advance doubles the previous record for field-effect electronic device mobility and enables access to new regimes of quantum transport and applications that were previously unfathomable due to mobility limitations.
Paper Structure (4 figures)

This paper contains 4 figures.

Figures (4)

  • Figure 1: Design of the field-effect gates assembly and representation of the flip-chip fabrication process. (A) Left panel: optical image of gates fabricated using electron beam lithography (EBL). Right panel: optical image of a different gate assembly design fabricated with photolithography. The gate assembly on the left, denoted FPI, consists of a set of plunger gates with a 2 $\mu$m tip separation, positioned between two quantum point contacts (QPCs) with a 400 nm tip separation. The right assembly, denoted TRP, comprises three parallel QPCs separated by 3.5 $\mu$m, each with a 400 nm tip separation. (B) Device fabrication schematic showing that metallic gates were fabricated on a sapphire substrate using EBL prior to mechanical assembly with the GaAs/AlGaAs wafer hosting the 2DEG. The wafer itself is unprocessed except for ohmic contacts formed by diffusion.
  • Figure 2: Electron density and mobility measurements for the highest electron mobility flip-chip device fabricated. (A) Longitudinal resistance $R_{xx}$ of the flip-chip device with the FPI gate assembly (see Fig. \ref{['fig:1']}) mounted on GaAs/AlGaAs wafer #P5-4-21.1, measured at 14 mK versus time. The dotted line shows the computed average with a filter of $R_{xx} = 4.45(10)$$\Omega$. (B) Hall resistance $R_{xy}$ of the same device versus magnetic field. The electron density was extracted from the linear fit (dotted line), yielding a value of $1.47(1)\times 10^{11}$ cm$^{-2}$, corresponding to an electron mobility of $44(2)\times 10^6$ cm$^2$/(Vs). This mobility is in excellent agreement with prior measurements at Princeton by the GaAs/AlGaAs growth team at $\sim$300 mK.
  • Figure 3: Conductance versus gate voltage for three distinct flip-chip devices.(A) Conductance $G$ versus gate voltages $V_g$ for a flip-chip device with TRP gates mounted on GaAs/AlGaAs 2DEG wafer #3-11-10.2, with all gates activated at the same voltage $V_g$. (B) Conductance $G$ versus gate voltages $V_g$ for a second device based on the same TRP gate design but mounted on a different piece from the same wafer, with a 40 nm thick Al$_2$O$_3$ layer deposited via ALD as a final capping layer, with four out of six gates activated at the same voltage $V_g$ (shown by blue false coloring). (C) Conductance $G$ versus gate voltages $V_g$ for a flip-chip device with FPI gates mounted on ultra-high mobility GaAs/AlGaAs 2DEG wafer (#P5-4-21.1), with four out of six gates activated at the same voltage $V_g$ (shown by blue false coloring). Optical photographs of the gate assemblies for each measured device are shown in the inset of each panel. In all panels, the electron mobilities measured in the same cooldowns are shown. All data was taken at $\sim$$300$ mK.
  • Figure 4: Conductance versus gates voltage in a magnetic field. Same electronic device as shown in Fig. \ref{['fig:3']} C (FPI + #P5.4.21.1) but measured at 14 mK temperature and in a magnetic field $B=1.958$ T, corresponding to a filling factor of $\nu=3.11$. All gates were activated with an equipotential voltage $V_g$ in this measurement, as shown by the blue false coloring of the gates in the inset.