Pipeline Automation Framework for Reusable High-throughput Network Applications on FPGA

TL;DR

This work introduces the Pipeline Automation Framework (PAF), a decoupled, pipeline-oriented design methodology that enables architectural parameterization of FPGA-based network pipelines. By modeling synchronization as TimeZones and relations within a graph, PAF separates functional pipeline descriptions from target-specific timing and protocol concerns, allowing automated resolution strategies to balance latency and resource usage. The framework supports multiple elaboration-time configurations, including protocol choices (e.g., RawIO vs Ready/Valid) and hardware primitives (wire, register, FIFO), and provides an analysis suite to explore design space efficiently. An industrial use-case on tree-based packet classifiers demonstrates near-baseline resource usage with significant gains in reusability and maintainability, validating zero-cost abstractions and the practical impact for agile network infrastructures. The work points to future expansion toward variable-latency propagations and cross-level automation, further easing cross-target design and rapid adaptation to evolving requirements.

Abstract

In a context of ever-growing worldwide communication traffic, cloud service providers aim at deploying scalable infrastructures to address heterogeneous needs. Part of the network infrastructure, FPGAs are tailored to guarantee low-latency and high-throughput packet processing. However, slowness of the hardware design process impairs FPGA ability to be part of an agile infrastructure under constant evolution, from incident response to long-term transformation. Deploying and maintaining network functionalities across a wide variety of FPGAs raises the need to fine-tune hardware designs for several FPGA targets. To address this issue, we introduce PAF, an open-source architectural parameterization framework based on a pipeline-oriented design methodology. PAF (Pipeline Automation Framework) implementation is based on Chisel, a Scala-embedded Hardware Construction Language (HCL), that we leverage to interface with circuit elaboration. Applied to industrial network packet classification systems, PAF demonstrates efficient parameterization abilities, enabling to reuse and optimize the same pipelined design on several FPGAs. In addition, PAF focuses the pipeline description on the architectural intent, incidentally reducing the number of lines of code to express complex functionalities. Finally, PAF confirms that automation does not imply any loss of tight control on the architecture by achieving on par performance and resource usage with equivalent exhaustively described implementations.

Figures (12)

• Figure 1: Network application pipelined representation
• Figure 2: Potential integration issue with submodule latency evolution
• Figure 3: Decoupled Pipeline Description Methodology
• Figure 4: Design Intent
• Figure 5: Generation Intent with Additional Signal e