An Ion-Intercalation Memristor for Enabling Full Parallel Writing in Crossbar Networks
Tingwei Zhang, Jiahui Liu, David Allstot, Huaping Liu
TL;DR
This work tackles the sneak-path bottleneck in memristor crossbars by introducing a four-terminal ion-intercalation memristor with orthogonal read/write paths, enabling true parallel writes. By leveraging reversible Li+ intercalation in a polymer buffer, the device achieves continuous, analog resistance programming governed by $M(q)=K/q$ and a bulk-doping mechanism, decoupling read and write access. Experimental demonstrations with two prototypes show a wide resistance range, reversible programming, and retention behaviors, supporting the architecture's viability for scalable in-memory computing. The authors argue that architectural read/write isolation eliminates sneak paths and discuss the inevitable routing overhead required to realize deterministic parallelism at scale.
Abstract
Crossbar architectures have long been seen as a promising foundation for in-memory computing, using memristor arrays for high-density, energy-efficient analog computation. However, this conventional architecture suffers from a fundamental limitation: the inability to perform parallel write operations due to the sneak path problem. This arises from the structural overlap of read and write paths, forcing sequential or semi-parallel updates and severely limiting scalability. To address this, we introduce a new memristor design that decouples read and write operations at the device level. This design enables orthogonal conductive paths, and employs a reversible ion doping mechanism, inspired by lithium-ion battery principles, to modulate resistance states independently of computation. Fabricated devices exhibit near-ideal memristive characteristics and stable performance under isolated read/write conditions.