Optimal control of bit erasure in stochastic random access memory

TL;DR

The paper addresses the thermodynamic cost of finite-time bit erasure in realistic CMOS RAM implemented as DRAM and SRAM, showing that operation away from equilibrium can substantially affect energy dissipation. It combines stochastic thermodynamics with differentiable optimization, leveraging a Markovian CMOS RAM model and mean-field dynamics to derive time-dependent control protocols for wordline and bitline voltages. The key findings are that DRAM dissipates least energy in the quasistatic limit while SRAM exhibits a housekeeping-heat-limited optimum at intermediate operation times, with mean-field theory accurately capturing these trends alongside kinetic Monte Carlo simulations. The work provides a numerically robust framework for designing thermodynamically advantageous operation of nanoscale circuits and can be extended to larger CMOS networks.

Abstract

Energy costs of information processing are growing exponentially. Bit erasure is a key problem in this energy-information nexus, and a number of seminal relationships have been deduced regarding the relationship between thermodynamic costs and memory storage. To continue making progress in the modern era, however, requires confronting thermodynamic costs in realistic physical systems which operate away from equilibrium. Here, we explore the thermodynamic costs of bit erasure in a complementary metal oxide semiconductor model of two types of random access memory. We find dynamic random access memory dissipates the least amount of energy when operated in the quasistatic limit, where errors are also minimized. By contrast, static random access memory is most efficiently operated in finite time due to the energy required to maintain the state of the bit. We demonstrate a numerically robust optimization scheme using mean field theory and automatic differentiation, finding optimal protocols compatible with electrical engineering insights. These results provide a framework for operating realistic circuits in thermodynamically advantageous ways.

Figures (9)

• Figure 1: Schematic of bit erasure and related timescales. (a) Controlled bit erasure, driven by time-dependent $V_\mathrm{w}(t),V_\mathrm{b}(t)$ to 0 state. (b) Dynamic random access memory (DRAM) circuit. (c) Static random access memory (SRAM) circuit. (d) Idealized trajectory showing evolution of bit state $V_\mathrm{o}(t)$ (blue) in response to control $V_\mathrm{b}(t)$ (orange). (e) Probability distribution of bit state before (orange) and after (blue) erasure, with threshold voltage $V^*$ defining 0 state. (f) Relevant timescales for electron residence time in transistor $\tau_\mathrm{t}$, operation time $\tau_\mathrm{op}$, and stochastic error time $\tau_\mathrm{err}$.
• Figure 2: Dynamic random access memory (DRAM) phenomenology. (a) The DRAM circuit consisting of an ideal bitline electrode at voltage $V_\mathrm{b}$, an access transistor controlled by the wordline voltage $V_\mathrm{w}$, and a capacitor with output voltage $V_\mathrm{o}$ indicating the bit state. (b) Average current across the transistor at constant values of $V_\mathrm{w}$ and different driving voltages $V_\mathrm{d}$. (c) Example trajectories of bit erasure starting in logical 1 (orange) or 0 (blue) compared to the estimate from mean field theory (black), for the output voltage (top) and heat (bottom).
• Figure 3: Heat-accuracy tradeoffs observed in DRAM, averaged over starting states 0 and 1. (a) Error and (b) dissipated heat for two driving voltages $V_\mathrm{d}/V_\mathrm{th}=3$ (green circles) and $V_\mathrm{d}/V_\mathrm{th}=6$ (purple squares) across operation times. (c) and (d) Representative trajectories and optimal protocols for short and long operation times, respectively, with stochastic dynamics starting in logical 1 (orange) or 0 (blue) state consistent with mean field dynamics (black).
• Figure 4: Static random access memory (SRAM) phenomenology. (a) One of two coupled not gates in the SRAM circuit. It contains an ideal bitline electrode at $V_\mathrm{b}$, an access transistor controlled by the wordline $V_\mathrm{w}$, and a capacitor with output voltage $V_\mathrm{o}$ indicating the bit state like in DRAM, but the capacitor is additionally connected to ideal source $V_\mathrm{s}$ and drain $V_\mathrm{d}$ electrodes with a nonequilibrium bias across them. (b) Pitchfork bifurcation behavior as a function of driving voltage $V_\mathrm{d}$. Memory is stored when bistability emerges above a critical voltage $V_\mathrm{d}^* \approx 2.5$. (c) Example trajectories of bit erasure starting in logical 1 (orange) or 0 (blue) compared to the estimate from mean field theory (black) for coupled output voltages (top, middle) and dissipated heat (bottom).
• Figure 5: Heat-accuracy tradeoffs observed in SRAM, averaged over starting states 0 and 1. (a) Error and (b) dissipated heat for two driving voltages $V_\mathrm{d}/V_\mathrm{th}=3$ (green circles) and $V_\mathrm{d}/V_\mathrm{th}=6$ (purple squares) across operation times. (c) and (d) Representative trajectories and optimal protocols for short and long operation times, respectively, with stochastic dynamics starting in logical 1 (orange) or 0 (blue) state consistent with mean field dynamics (black).