GNN-based Path-aware multi-view Circuit Learning for Technology Mapping

TL;DR

This paper tackles the persistent gap between technology-agnostic pre-mapping delay models and actual post-mapping timing in circuit technology mapping. It proposes GPA, a GNN-based path-aware multi-view framework that fuses AIG-based functional encoding, post-mapping context, and path-aware Transformer pooling to predict post-mapping cut delays from real critical-path data. Trained on real delays from critical paths, GPA markedly improves delay outcomes, outperforming traditional techmap and MCH methods by up to nearly 20% and surpassing the prior ML-based SLAP by about 4% on 19 EPFL benchmarks, while maintaining area efficiency. The approach demonstrates the practical potential of integrating path-aware, data-driven delay predictions into mapping engines, with extensions to mixed-structure representations (XMG) and broader post-mapping information as future work.

Abstract

Traditional technology mapping suffers from systemic inaccuracies in delay estimation due to its reliance on abstract, technology-agnostic delay models that fail to capture the nuanced timing behavior behavior of real post-mapping circuits. To address this fundamental limitation, we introduce GPA(graph neural network (GNN)-based Path-Aware multi-view circuit learning), a novel GNN framework that learns precise, data-driven delay predictions by synergistically fusing three complementary views of circuit structure: And-Inverter Graphs (AIGs)-based functional encoding, post-mapping technology emphasizes critical timing paths. Trained exclusively on real cell delays extracted from critical paths of industrial-grade post-mapping netlists, GPA learns to classify cut delays with unprecedented accuracy, directly informing smarter mapping decisions. Evaluated on the 19 EPFL combinational benchmarks, GPA achieves 19.9%, 2.1% and 4.1% average delay reduction over the conventional heuristics methods (techmap, MCH) and the prior state-of-the-art ML-based approach SLAP, respectively-without compromising area efficiency.

Figures (5)

• Figure 1: Experimental Results by Random Cuts Selection
• Figure 2: Model overview of GPA: First, the AIG Encoder and PM Encoder extract node embeddings from the logic network and technology-specific constraints, respectively, optimized via structural mask modeling and functional probability prediction tasks. Then, the Path-aware Transformer Pooling module aggregates context from the leaf nodes of a target cut. Finally, an MLP classifier utilizes the generated cut embedding to predict the post-mapping delay class.
• Figure 3: Work Flow of the proposed framework: First, the technology-independent AIG netlist is input into the logic synthesis tool to generate candidate cut sets. Then, the pre-trained GPA model performs inference on these cuts to predict their post-mapping delay classes. Finally, these predictions serve as guidance (cost metric) for the mapper's dynamic programming algorithm to select the optimal cuts, yielding the final technology-mapped results.
• Figure 4: Cell delay distribution
• Figure 5: Training process of GPA