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Bit-Efficient Quantisation for Two-Channel Modulo-Sampling Systems

Wenyi Yan, Zeyuan Li, Lu Gan, Honqing Liu, Guoquan Li

TL;DR

The paper tackles bitrate inefficiency in two-channel modulo-ADC systems by introducing ECRT, a bit-efficient quantisation that transmits one channel output together with a compact inter-channel difference. It provides formal guarantees showing the bitrate overhead is only $1$–$2$ bits per sample relative to conventional high-dynamic-range ADCs, while maintaining stable recovery under bounded noise. The approach leverages the integer-valued inter-channel difference $d[k]=(y_2[k]-y_1[k])/\\varepsilon$ and a fixed-difference bit budget $b_d=\\lceil \\log_2( au_1+\\tau_2) \\rceil$, achieving $B_{\\mathrm{ECRT}}=b+b_d$ and a recovery bound $|\\hat{g}_{\\mathrm{ECRT}}[k]-g[k]| \\le \\|e_1\\|_\\infty + \\Delta_1/2^{b+1}$. Simulations and hardware experiments show substantial bitrate savings over prior modulo-sampling schemes with comparable reconstruction accuracy, validating ECRT as a practical, Nyquist-rate, bitrate-efficient solution for high-dynamic-range sensing. The results imply a viable path to high-resolution, bandwidth-efficient modulo ADCs in resource-constrained systems.

Abstract

Two-channel modulo analog-to-digital converters (ADCs) enable high-dynamic-range signal sensing at the Nyquist rate per channel, but existing designs quantise both channel outputs independently, incurring redundant bitrate costs. This paper proposes a bit-efficient quantisation scheme that exploits the integer-valued structure of inter-channel differences, transmitting one quantised channel output together with a compact difference index. We prove that this approach requires only 1-2 bits per signal sample overhead relative to conventional ADCs, despite operating with a much smaller per-channel dynamic range. Simulations confirm the theoretical error bounds and bitrate analysis, while hardware experiments demonstrate substantial bitrate savings compared with existing modulo sampling schemes, while maintaining comparable reconstruction accuracy. These results highlight a practical path towards high-resolution, bandwidth-efficient modulo ADCs for bitrate-constrained systems.

Bit-Efficient Quantisation for Two-Channel Modulo-Sampling Systems

TL;DR

The paper tackles bitrate inefficiency in two-channel modulo-ADC systems by introducing ECRT, a bit-efficient quantisation that transmits one channel output together with a compact inter-channel difference. It provides formal guarantees showing the bitrate overhead is only – bits per sample relative to conventional high-dynamic-range ADCs, while maintaining stable recovery under bounded noise. The approach leverages the integer-valued inter-channel difference and a fixed-difference bit budget , achieving and a recovery bound . Simulations and hardware experiments show substantial bitrate savings over prior modulo-sampling schemes with comparable reconstruction accuracy, validating ECRT as a practical, Nyquist-rate, bitrate-efficient solution for high-dynamic-range sensing. The results imply a viable path to high-resolution, bandwidth-efficient modulo ADCs in resource-constrained systems.

Abstract

Two-channel modulo analog-to-digital converters (ADCs) enable high-dynamic-range signal sensing at the Nyquist rate per channel, but existing designs quantise both channel outputs independently, incurring redundant bitrate costs. This paper proposes a bit-efficient quantisation scheme that exploits the integer-valued structure of inter-channel differences, transmitting one quantised channel output together with a compact difference index. We prove that this approach requires only 1-2 bits per signal sample overhead relative to conventional ADCs, despite operating with a much smaller per-channel dynamic range. Simulations confirm the theoretical error bounds and bitrate analysis, while hardware experiments demonstrate substantial bitrate savings compared with existing modulo sampling schemes, while maintaining comparable reconstruction accuracy. These results highlight a practical path towards high-resolution, bandwidth-efficient modulo ADCs for bitrate-constrained systems.
Paper Structure (7 sections, 2 theorems, 27 equations, 2 figures, 2 tables, 1 algorithm)

This paper contains 7 sections, 2 theorems, 27 equations, 2 figures, 2 tables, 1 algorithm.

Table of Contents

  1. Introduction
  2. Background and Motivation
  3. Proposed Bit-Efficient Two-Channel Design
  4. System Model
  5. Comparison with other schemes
  6. Simulation and Hardware Results
  7. Conclusion

Key Result

Theorem 1

Consider the two-channel modulo sampling system in Fig. fig:archi with dynamic ranges $\Delta_\ell=\tau_\ell\varepsilon$, $\ell=1,2$, where $\varepsilon>0$ and $\tau_1,\tau_2$ are relatively coprime integers satisfying $2\le\tau_1<\tau_2$. For an input signal $g(t)$ with $\|g(t)\|_\infty\le \frac{\t the sampled difference signal, where $d[k]=(y_2[k]-y_1[k])/\varepsilon$ is the normalised differenc

Figures (2)

  • Figure 1: Proposed bit-efficient two-channel modulo-ADC architecture. Channel 1 quantises $y_1(t)$, while Channel 2 quantises the scaled signal $\tilde{s}(t)$.
  • Figure 2: MAE vs. transmission bitrate for conventional ADC, RCRT, and the proposed ECRT.

Theorems & Definitions (5)

  • Theorem 1: ECRT: quantisation and stable recovery
  • Corollary 1
  • Remark
  • Remark
  • Remark