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The Quest for Reliable AI Accelerators: Cross-Layer Evaluation and Design Optimization

Meng Li, Tong Xie, Zuodong Zhang, Runsheng Wang

TL;DR

This paper systematically presents a series of reliability-aware accelerator designs, encompassing aging and variation-aware dynamic timing analyzer, accelerator dataflow optimization using critical input pattern reduction, and resilience characterization and novel architecture design for large language models (LLMs).

Abstract

As the CMOS technology pushes to the nanoscale, aging effects and process variations have become increasingly pronounced, posing significant reliability challenges for AI accelerators. Traditional guardband-based design approaches, which rely on pessimistic timing margin, sacrifice significant performance and computational efficiency, rendering them inadequate for high-performance AI computing demands. Current reliability-aware AI accelerator design faces two core challenges: (1) the lack of systematic cross-layer analysis tools to capture coupling reliability effects across device, circuit, architecture, and application layers; and (2) the fundamental trade-off between conventional reliability optimization and computational efficiency. To address these challenges, this paper systematically presents a series of reliability-aware accelerator designs, encompassing (1) aging and variation-aware dynamic timing analyzer, (2) accelerator dataflow optimization using critical input pattern reduction, and (3) resilience characterization and novel architecture design for large language models (LLMs). By tightly integrating cross-layer reliability modeling and AI workload characteristics, these co-optimization approaches effectively achieve reliable and efficient AI acceleration.

The Quest for Reliable AI Accelerators: Cross-Layer Evaluation and Design Optimization

TL;DR

This paper systematically presents a series of reliability-aware accelerator designs, encompassing aging and variation-aware dynamic timing analyzer, accelerator dataflow optimization using critical input pattern reduction, and resilience characterization and novel architecture design for large language models (LLMs).

Abstract

As the CMOS technology pushes to the nanoscale, aging effects and process variations have become increasingly pronounced, posing significant reliability challenges for AI accelerators. Traditional guardband-based design approaches, which rely on pessimistic timing margin, sacrifice significant performance and computational efficiency, rendering them inadequate for high-performance AI computing demands. Current reliability-aware AI accelerator design faces two core challenges: (1) the lack of systematic cross-layer analysis tools to capture coupling reliability effects across device, circuit, architecture, and application layers; and (2) the fundamental trade-off between conventional reliability optimization and computational efficiency. To address these challenges, this paper systematically presents a series of reliability-aware accelerator designs, encompassing (1) aging and variation-aware dynamic timing analyzer, (2) accelerator dataflow optimization using critical input pattern reduction, and (3) resilience characterization and novel architecture design for large language models (LLMs). By tightly integrating cross-layer reliability modeling and AI workload characteristics, these co-optimization approaches effectively achieve reliable and efficient AI acceleration.
Paper Structure (14 sections, 9 figures, 1 table)

This paper contains 14 sections, 9 figures, 1 table.

Table of Contents

  1. Introduction
  2. Aging- and Variation-Aware DTA
  3. Motivation
  4. AVATAR Algorithm
  5. Experiments
  6. Critical Input Pattern Reduction
  7. Computing Sequence and Timing Error
  8. Input Channel Reordering and Output Channel Clustering
  9. Experiments
  10. Statistical Algorithm-based Fault Tolerance
  11. LLM Resilience Characterization
  12. Statistical Algorithm-Based Fault Tolerance
  13. Experiments
  14. Conclusion

Figures (9)

  • Figure 1: Overview of our recent works.
  • Figure 2: Aging- and variation-aware DTA flow of AVATAR.
  • Figure 3: A 1$\times$4 convolution calculated in different orders. Reordering weights does not change the computing result, but avoids the critical input pattern.
  • Figure 4: (a) Input channel reordering. (b) Output channel clustering.
  • Figure 5: Timing error rate comparison for different reliability-enhanced algorithms on ResNet-18 and VGG-16.
  • ...and 4 more figures