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GIC-DLC: Differentiable Logic Circuits for Hardware-Friendly Grayscale Image Compression

Till Aczel, David F. Jenny, Simon Bührer, Andreas Plesner, Antonio Di Maio, Roger Wattenhofer

TL;DR

The paper tackles the trade-off between compression performance and hardware efficiency in neural image codecs for edge devices. It introduces GIC-DLC, a grayscale image codec that uses Differentiable Logic Circuits (DLCs) implemented as NeuraLUTs to predict per-pixel distributions within a multi-resolution hierarchical framework, combining UPS and ARM modules with ANS-based entropy coding. By training end-to-end and deploying on hardware-friendly LUT networks, the method achieves high compression efficiency while dramatically reducing energy consumption and latency compared to traditional codecs, demonstrated on grayscale datasets such as EMNIST. This work shows the practicality of hardware-friendly learned compression for energy-constrained environments and points to future extensions to RGB distributions and FPGA implementations for real-world deployment.

Abstract

Neural image codecs achieve higher compression ratios than traditional hand-crafted methods such as PNG or JPEG-XL, but often incur substantial computational overhead, limiting their deployment on energy-constrained devices such as smartphones, cameras, and drones. We propose Grayscale Image Compression with Differentiable Logic Circuits (GIC-DLC), a hardware-aware codec where we train lookup tables to combine the flexibility of neural networks with the efficiency of Boolean operations. Experiments on grayscale benchmark datasets show that GIC-DLC outperforms traditional codecs in compression efficiency while allowing substantial reductions in energy consumption and latency. These results demonstrate that learned compression can be hardware-friendly, offering a promising direction for low-power image compression on edge devices.

GIC-DLC: Differentiable Logic Circuits for Hardware-Friendly Grayscale Image Compression

TL;DR

The paper tackles the trade-off between compression performance and hardware efficiency in neural image codecs for edge devices. It introduces GIC-DLC, a grayscale image codec that uses Differentiable Logic Circuits (DLCs) implemented as NeuraLUTs to predict per-pixel distributions within a multi-resolution hierarchical framework, combining UPS and ARM modules with ANS-based entropy coding. By training end-to-end and deploying on hardware-friendly LUT networks, the method achieves high compression efficiency while dramatically reducing energy consumption and latency compared to traditional codecs, demonstrated on grayscale datasets such as EMNIST. This work shows the practicality of hardware-friendly learned compression for energy-constrained environments and points to future extensions to RGB distributions and FPGA implementations for real-world deployment.

Abstract

Neural image codecs achieve higher compression ratios than traditional hand-crafted methods such as PNG or JPEG-XL, but often incur substantial computational overhead, limiting their deployment on energy-constrained devices such as smartphones, cameras, and drones. We propose Grayscale Image Compression with Differentiable Logic Circuits (GIC-DLC), a hardware-aware codec where we train lookup tables to combine the flexibility of neural networks with the efficiency of Boolean operations. Experiments on grayscale benchmark datasets show that GIC-DLC outperforms traditional codecs in compression efficiency while allowing substantial reductions in energy consumption and latency. These results demonstrate that learned compression can be hardware-friendly, offering a promising direction for low-power image compression on edge devices.
Paper Structure (22 sections, 6 equations, 3 figures, 2 tables)

This paper contains 22 sections, 6 equations, 3 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Related Work
  3. Method
  4. Hierarchical Compression Framework
  5. Upsampling Model (UPS)
  6. Autoregressive Model (ARM)
  7. Differentiable Logic Circuits (DLCs)
  8. Experiment Setup
  9. Results Analysis
  10. Discussion
  11. Energy Usage and Latency
  12. Potential Applications
  13. Future Work
  14. Conclusion
  15. Experiment Setup Detailed
  16. ...and 7 more sections

Figures (3)

  • Figure 1: Overview of the decoding architecture. Top: the image is upsampled $L=2$ times, with each higher-resolution level decoded conditioned on the lower-resolution one. Bottom: at each resolution, an upsampling model (UPS) and an autoregressive model (ARM), both implemented as NeuraLUT networks, produce predictions used for entropy decoding. The UPS model outputs point estimates for the upsampled pixels (conditioned on the lower-resolution reconstruction), which serve as priors for pixels that are not yet decoded. The ARM predicts per-pixel, Laplace parameters conditioned on the local, already-decoded context; when a pixel is not yet decoded, the ARM uses the UPS point estimate as its prior. Decoding proceeds from the coarsest to the finest resolution; encoding follows the reverse order.
  • Figure 2: Comparison of theoretical bits per pixel (bpp-theoretical) across resolution levels (left) and root mean squared error (RMSE) of upsampling (right) on the EMNIST test set. The left plot shows that most bits are concentrated in the highest resolution, while the right plot highlights the superior accuracy of the learned upsampling.
  • Figure 3: Examples from the EMNIST ByClass test set illustrating compression difficulty. Left: images that are easy to encode, such as the letter I, which are straight and simple. Right: images that are hard to encode, such as the number 8 and other characters with unusual or complex shapes.