A flexible language model-assisted electronic design automation framework

TL;DR

A versatile framework that uses LLMs to generate files compatible with commercial EDA tools and optimise designs using power-performance-area reports is proposed, guiding the LLMs with tool constraints and feedback from design outputs to meet tool requirements and user specifications.

Abstract

Large language models (LLMs) are transforming electronic design automation (EDA) by enhancing design stages such as schematic design, simulation, netlist synthesis, and place-and-route. Existing methods primarily focus these optimisations within isolated open-source EDA tools and often lack the flexibility to handle multiple domains, such as analogue, digital, and radio-frequency design. In contrast, modern systems require to interface with commercial EDA environments, adhere to tool-specific operation rules, and incorporate feedback from design outcomes while supporting diverse design flows. We propose a versatile framework that uses LLMs to generate files compatible with commercial EDA tools and optimise designs using power-performance-area reports. This is accomplished by guiding the LLMs with tool constraints and feedback from design outputs to meet tool requirements and user specifications. Case studies on operational transconductance amplifiers, microstrip patch antennas, and FPGA circuits show that the framework is effective as an EDA-aware assistant, handling diverse design challenges reliably.

Figures (18)

• Figure 1: A block diagram of the LaMDA framework. a, The framework processes either a custom user prompt or a predefined prompt from a dataset. The custom user prompt includes design description and design objectives, such as area, delay, power constraints. The predefined prompt from a dataset may also include additional information, such as simulation stimuli. b, The Source File Generation module includes an LLM that provides source files for the EDA tool, such as analogue and RF netlists or Verilog scripts. The module also preprocesses input prompts to record the output token count and time corresponding to the LLM-generated response. c, The EDA tool is provided with source files from the LLM, generates the workspace, instantiates the design, runs simulations, and executes the design implementation. d, The PPA reports and log files are supplied to the Report Postprocessing module. Key log messages and information such as occupied area and power dissipation are extracted through a parser. The parsed information is logged and can be visualised for further data analysis. The framework supports two execution paths: termination of the process or continuation through additional optimisation cycles with LLM-assisted recommendations. In either case, the objectives specified in the input prompts are evaluated.
• Figure 2: Application of LaMDA in an analogue design flow example.a, Input prompt. Design a 5--transistor OTA using integer-micron sizing (L $\geq$ 1um) to achieve Gain $>$ 40 dB and PM $>$ 60 degrees. Set VDD = 5 V and sweep $V_{BIAS}$ (0.6V--2.5 V) while keeping power under 0.5 mW to target approx 1 MHz UGB with a small CL. b, Generated netlist. The netlist includes information about the device parameters ($W_{\mathrm{diff}}$, $L_{\mathrm{diff}}$, etc.) and includes necessary analysis commands and voltage sources, demonstrating the LLM's capability to generate functional SPICE code. The generated netlist is compatible with Cadence Virtuoso Spectre. LaMDA then performs 15 simulations, sweeping $V_{BIAS}$ across different values to evaluate the design and identify operating points that meet the initial objectives. c, The 5-transistor OTA circuit with an NMOS differential pair (M1, M2), PMOS diode-connected loads (M3, M4), and an NMOS tail current source (M5). d, OTA gain from simulations. The graph shows the reduced DC gain and increased UGB with increasing bias, illustrating the speed--gain trade-off. e, DC gain and phase margin across 15 sweeps. Gain decreases with increasing tail current, while PM remains more than $60^\circ$, confirming stability. f, UGB across 15 sweeps. UGB improves with iteration, but at the cost of steadily increasing power, with bandwidth gains gradually saturating at later sweeps.
• Figure 3: Application of LaMDA in an RF design flow example.a, Input prompt. The user specifies the design of a microstrip patch antenna on an FR-4 substrate, with an operating frequency of $f=2.4$ GHz and a target reflection coefficient $S_{11} < -10\,\mathrm{dB}$. b, Netlist generated by the LLM, which includes the antenna parameters in the form of transmission line components, the microstrip substrate parameters, and the S-parameters simulation setup. The generated netlist is compatible with Keysight ADS. Of 10 predefined iterations, iteration 1 failed due to a component's terminal specification error, therefore, iteration 2 is considered as the initial valid iteration. The target performance was achieved at iteration 9 and further improved at iteration 10. The reported netlist refers to the final iteration. c, Graph-based visualisation of the netlist to ensure correct connectivity between components. d, The equivalent antenna layout generated by Keysight ADS. e, Reflection coefficient from 2D S-parameters simulation. We report iterations 1, 2, 5, 9, 10. Each curve consists of 101 frequency-S$_{11}$ pairs. f, Normalised far-field H-plane ($\phi=90^{\circ}$) radiation pattern of the patch antenna for the last design iteration, generated from a 3D EM simulation. The curve consists of 62 $\theta-\vert E(\theta)\vert$ pairs.
• Figure 4: Application of LaMDA in an FPGA design flow example.a, Input prompt. The user requires a 3-state FSM, operating at a frequency of 1000 MHz and being implemented without LUTs. The module header, reporting input and output ports, is also provided. b, Verilog script generated by the LLM. c, LLM response time in seconds. The LaMDA framework runs the full ResBench datasetGuo_2025 that consists of 56 problems across 12 categories. The 3-state FSM in a,b is one of the problems. We run each problem 5 times to take into account the LLM randomness. On average, the LLM response time spans from 2 seconds (category: bitwise and logical operations) to 7 seconds (category: pipelining). d, Pass rate related to the implementation step on FPGA. For each category-problem ID pair, we report the number of successful implementation runs out of 5. Different categories contain different numbers of problems, therefore, grey cells are used to pad the table for visual consistency. e, Pass rate related to the LUT objective. For each category-problem ID pair, we report the number of successful runs, out of 5, where the LUT objective is met.
• Figure 5: Comparative analysis across different case studies (OTA, RF antenna, and FSM design) and LLM models (OpenAI GPT-4o-mini, GPT-4o, and o1).a, Percentage deviation from the target performance. In the case of the OTA, we required $gain > 40$ dB. In the case of the RF antenna, we required $S_{11} \leq -10$ dB at a frequency of $f=2.4$ GHz. In the case of the FSM, we required a clock frequency $f \geq 1$ GHz. We reported the best deviation across the attempts. b, LLM response time. In the case of the OTA, we reported statistical results across 5 runs per model. In the case of the RF antenna, we reported statistical results across 10 iterations. In the case of the FSM, we reported statistical results across 5 runs per model. c, LLM token count associated to the output messages.