'1'-bit Count-based Sorting Unit to Reduce Link Power in DNN Accelerators

TL;DR

This work tackles the high interconnect power in DNN accelerators by ordering data according to $1$-bit counts to reduce bit transitions on links. It introduces a hardware, comparison-free popcount-sorting unit for CNNs and improves efficiency with approximate bucketization, trading some ordering precision for substantial area and power reductions. The ACC-PSU baseline and the APP-PSU approximate sorter demonstrate up to $35.4\%$ area reduction and $37.3\%$ power reduction, while maintaining about $95.5\%$ BT reduction relative to the precise implementation, with additional $16.48\%$ link-power savings observed in post-layout analysis. These results support practical deployment in NoC-based accelerators and point to scalable benefits for larger models and multi-hop interconnects.

Abstract

Interconnect power consumption remains a bottleneck in Deep Neural Network (DNN) accelerators. While ordering data based on '1'-bit counts can mitigate this via reduced switching activity, practical hardware sorting implementations remain underexplored. This work proposes the hardware implementation of a comparison-free sorting unit optimized for Convolutional Neural Networks (CNN). By leveraging approximate computing to group population counts into coarse-grained buckets, our design achieves hardware area reductions while preserving the link power benefits of data reordering. Our approximate sorting unit achieves up to 35.4% area reduction while maintaining 19.50\% BT reduction compared to 20.42% of precise implementation.

Figures (7)

• Figure 1: Architecture of the pop-sort unit with an example data flow.
• Figure 2: Examples of ordered on 128-bit links after our APP-PSU.
• Figure 3: Platform with sorting units and PEs for convolution and pooling layers.
• Figure 4: QuestaSim waveform of APP-PSU.
• Figure 5: Area breakdown of different Sorting Unit designs.