3D Stacked Surface-Code Architecture for Measurement-Free Fault-Tolerant Quantum Error Correction

TL;DR

This work tackles the readout bottleneck in superconducting quantum processors by introducing a 3D stacked surface-code architecture for measurement-free fault-tolerant quantum error correction (MFEC). By leveraging vertical couplers to enable transversal inter-layer operations in constant depth, the architecture eliminates the $O(d)$ SWAP routing overhead that plagues planar MFEC, while preserving local 2D stabilizer checks. A fault-tolerant MFEC protocol is embedded in this 3D stack and analyzed under a decoherence-based noise model, showing logical error rates orders of magnitude below both standard measurement-based surface codes and 2D MFEC variants in regimes with slow, noisy measurements. The results identify 3D integration as a practical enabler for scalable measurement-free fault tolerance, with significant implications for superconducting qubit platforms where mid-circuit measurements are costly.

Abstract

Mid-circuit measurements are a major bottleneck for superconducting quantum processors because they are slower and noisier than gates. Measurement-free quantum error correction (mfec) replaces repeated measurements and classical feed-forward by coherent quantum feedback, but existing mfec protocols suffer from severe connectivity overhead when mapped to planar surface-code architectures: transversal interactions between logical patches require SWAP chains of length $O(d)$ in the code distance, which increase depth and generate hook errors. This work introduces a 3D stacked surface-code architecture for measurement-free fault-tolerant quantum error correction that removes this connectivity bottleneck. Vertical transversal couplers between aligned surface-code patches enable coherent parity mapping and feedback with zero SWAP overhead, realizing constant-depth $O(1)$ inter-layer operations in d while preserving local 2D stabilizer checks. A fault-tolerant mfec protocol for the surface code is constructed that suppresses hook errors under realistic noise. An analytical performance model shows that the 3D architecture overcomes the readout error floor and achieves logical error rates orders of magnitude below both standard measurement-based surface codes and 2D mfec variants in regimes with slow, noisy measurements, identifying 3D integration as a key enabler for scalable measurement-free fault tolerance.

Figures (8)

• Figure 1: Routing overhead for planar MFEC surface codes. On a 2D nearest-neighbor layout, transversal coupling between a data patch and a logical ancilla patch requires SWAP-based routing with depth $O(d)$ for code distance $d$, increasing circuit depth and idling overhead.
• Figure 2: Proposed 3D stacked surface-code architecture. Three distance-$d$ rotated surface-code patches are stacked vertically. The middle layer hosts the data block $\left|{\psi}\right\rangle_L$, while the top and bottom layers are logical ancillas prepared in $\left|{0}\right\rangle_L$ and $\left|{+}\right\rangle_L$ for $Z$- and $X$-error correction, respectively. Vertical couplers enable transversal inter-layer coupling in constant depth with respect to $d$, removing the $O(d)$ SWAP-routing overhead required in planar 2D NN layouts.
• Figure 3: Logical error per EC cycle as a function of the decoherence ratio $R_{\mathrm{decoh}} = p_{\mathrm{decoh}}(t_{\mathrm{m}};T_1,T_2)/p_{\mathrm{decoh}}(t_{\mathrm{idle,op}};T_1,T_2)$ at fixed coherence times $(T_1,T_2)=(200~\mu\mathrm{s},150~\mu\mathrm{s})$, for distances $d\in\{3,7,11\}$. Solid: standard measurement-based surface code (SM-SC, Stim+MWPM). Dashed: proposed 3D MFEC-SC. Dotted: 2D MFEC-SC. The SM-SC degrades as measurements become relatively noisier, while the 3D MFEC-SC is essentially insensitive to $R_{\mathrm{decoh}}$. The 2D MFEC-SC remains significantly worse due to SWAP overhead.
• Figure 4: Logical error per EC cycle as a function of the overall noise scale $s$, which rescales $(T_1,T_2)\rightarrow(T_1^{\mathrm{(base)}}/s,T_2^{\mathrm{(base)}}/s)$, at fixed $R_{\mathrm{decoh}}=200$, for $d\in\{3,7,11\}$. For small and intermediate distances, the 3D MFEC-SC yields lower logical error than the SM-SC over a wide range of $s$, because it avoids noisy measurement windows. At larger distances and very high noise, the deeper MFEC cycles start to lose their advantage. The 2D MFEC-SC remains worse across all cases.
• Figure 5: Logical error per EC cycle as a function of code distance $d$ for the three architectures at a fixed working point $(R_{\mathrm{decoh}}=200,s=1)$. The 3D MFEC-SC (dashed) increases only mildly with $d$. The SM-SC (solid) initially improves with distance but quickly saturates due to measurement-induced errors. The 2D MFEC-SC (dotted) exhibits near-unit logical error for $d\ge 7$, highlighting the severe impact of SWAP overhead in planar MFEC implementations.