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Intrinsic Negative-U Centers in Freestanding LaAlO3/SrTiO3 Micro-membranes

Giulia Meucci, Pinelopi O. Konstantinopoulou, Thies Jansen, Gunjan Nagda, Damon J. Carrad, Emiliano Di Gennaro, Yu Chen, Nicola Manca, Nicolas Bergeal, Manuel Bibes, Alexei Kalaboukhov, Marco Salluzzo, Roberta Citro, Felix Trier, Nini Pryds, Fabio Miletto Granozio, Alessia Sambri, Thomas S. Jespersen

Abstract

The LaAlO3/SrTiO3 (LAO/STO) interface hosts a rich range of electronic phenomena, including unconventional electron pairing that in quantum dots gives rise to a negative effective charging energy U. Here, we show freestanding LAO/STO micro-membranes naturally hosting negative-U centers, where lateral confinement arises intrinsically, rather than from engineered nanostructures. These centers coexist with gate-tunable superconductivity and can remain stable upon thermal cycling from millikelvin temperatures to room temperature. Transport is in excellent agreement with calculations based on a negative-U Anderson model, and electrostatic simulations indicate characteristic center sizes of 20-80 nm. Our findings suggest that negative-U centers may arise from the intrinsic interfacial inhomogeneity typical of LAO/STO, and should therefore be considered a general feature of the LAO/STO interface. This could have important consequences for the microwave response of interfacial superconducting devices.

Intrinsic Negative-U Centers in Freestanding LaAlO3/SrTiO3 Micro-membranes

Abstract

The LaAlO3/SrTiO3 (LAO/STO) interface hosts a rich range of electronic phenomena, including unconventional electron pairing that in quantum dots gives rise to a negative effective charging energy U. Here, we show freestanding LAO/STO micro-membranes naturally hosting negative-U centers, where lateral confinement arises intrinsically, rather than from engineered nanostructures. These centers coexist with gate-tunable superconductivity and can remain stable upon thermal cycling from millikelvin temperatures to room temperature. Transport is in excellent agreement with calculations based on a negative-U Anderson model, and electrostatic simulations indicate characteristic center sizes of 20-80 nm. Our findings suggest that negative-U centers may arise from the intrinsic interfacial inhomogeneity typical of LAO/STO, and should therefore be considered a general feature of the LAO/STO interface. This could have important consequences for the microwave response of interfacial superconducting devices.
Paper Structure (11 sections, 5 figures)

This paper contains 11 sections, 5 figures.

Figures (5)

  • Figure 1: a False color scanning electron micrograph of a micro-membrane on SiO$_2$. b Device schematic together with a representation of the array of conductive puddles at the LAO/STO interface (not to scale). A nanometer-sized puddle (red) may represent the intrinsic origin of the observed negative-$U$ center. Inset: electrochemical potentials of the leads and transitions in a negative-$U$ center (black) and their evolution with magnetic field (red). c Differential resistance of Dev#1 as a function of $V_{\text{G}}$ and $I_{\text{SD}}$, with $B_{\parallel} = 25\ \mathrm{mT}$, to suppress Al-contact superconductivity ($T_{\text{c}}^{\text{Al}}\approx$1.2 K, $B_{\text{c}}^{\text{Al}}\approx$10 mT). d Gate dependence of switching current $I_{\text{s}}$, normal-state resistance $R_{\text{N}}$ and their product $I_{\text{s}} \cdot R_\text{N}$. e Normal-state conductance at $B_{\perp} = 0.5\ \mathrm{T}$ vs $V_\text{G}$ (black trace). The red trace shows the residual $\Delta G$ after background subtraction.
  • Figure 2: a Measured residual conductance, $\Delta G$, of Dev#1 as a function of $V_\text{G}$ and $V_\text{SD}$, at $B_{\perp} = 0.5\ \mathrm{T}$ (white dashed line in panel c). b Measured zero-bias $\Delta G$ versus $V_\text{G}$ and $B_{\parallel}$. The white curves show Lorentzian fits of a selected peak/peak pair at $B_{\parallel}=1.5,\ 2.5,\ 3.5,\ 4.5,\ 5.5\ \mathrm{T}$. The symbols correspond to those in Fig. 3. c Measured zero-bias $\Delta G$ versus $V_\text{G}$ and $B_{\perp}$. Panels b and c are shifted along $V_\text{G}$ by $\approx1.5\ \mathrm{V}$ and $\approx1.3\ \mathrm{V}$ respectively, to align the low-field peak center with panel a; the shift arises from device drift during measurements. d Simulated conductance versus $V_\text{G}$ and $V_\text{SD}$. e Simulated zero-bias conductance versus $V_\text{G}$ and $B_{\parallel}$. f Simulated zero-bias conductance versus $V_\text{G}$ and $B_{\perp}$. The numbers on panel e and f indicate the ground-state charge occupancy $\mathcal{N}$.
  • Figure 3: $B_{\parallel}$ dependence of the gate voltage separation between zero-bias conductance peaks in Dev#1 and Dev#2. The symbols correspond to those in Fig. 2b and S3. The pairing field, $B_{\text{P}}$, and the Landé $g$-factor, $g$, are extracted from linear fits (solid lines). For two peak pairs of Dev#2, data points at high fields (filled grey markers) are excluded from the fit. Note that in some cases the very low slope of $\Delta V_\text{G}(B)$ renders $B_\text{P}$ ill-defined.
  • Figure 4: a Estimated center diameter as a function of gate capacitance $C_\text{G}$ for a contact aspect ratio $w/w_\text{t} = 0.2$ and various vacuum thicknesses $t$. The inset shows a schematic of the simulated geometry (top and side views). b Estimated center diameter as a function of $C_\text{G}$ for a fixed vacuum thickness $t=50\ \mathrm{nm}$ and varying contact aspect ratios $w/w_\text{t}$.
  • Figure 5: a Thermal cycling sequence applied to Dev#1. b Residual conductance of Dev#1 after the first cool-down, after thermal cycling to 125 K, and after thermal cycling to room temperature with exposure to air, at $B_{\perp} = 0.5\ \mathrm{T}$. White dashed lines are guides to the eye.