Biological Intuition on Digital Hardware: An RTL Implementation of Poisson-Encoded SNNs for Static Image Classification

TL;DR

This paper presents the design and implementation of a cycle-accurate, hardware-oriented Spiking Neural Network (SNN) core implemented in SystemVerilog, and serves as a foundational building block for scalable, energy-efficient neuromorphic hardware on FPGA and ASIC platforms.

Abstract

The deployment of Artificial Intelligence on edge devices (TinyML) is often constrained by the high power consumption and latency associated with traditional Artificial Neural Networks (ANNs) and their reliance on intensive Matrix-Multiply (MAC) operations. Neuromorphic computing offers a compelling alternative by mimicking biological efficiency through event-driven processing. This paper presents the design and implementation of a cycle-accurate, hardware-oriented Spiking Neural Network (SNN) core implemented in SystemVerilog. Unlike conventional accelerators, this design utilizes a Leaky Integrate-and-Fire (LIF) neuron model powered by fixed-point arithmetic and bit-wise primitives (shifts and additions) to eliminate the need for complex floating-point hardware. The architecture features an on-chip Poisson encoder for stochastic spike generation and a novel active pruning mechanism that dynamically disables neurons post-classification to minimize dynamic power consumption. We demonstrate the hardware's efficacy through a fully connected layer implementation targeting digit classification. Simulation results indicate that the design achieves rapid convergence (89% accuracy) within limited timesteps while maintaining a significantly reduced computational footprint compared to traditional dense architectures. This work serves as a foundational building block for scalable, energy-efficient neuromorphic hardware on FPGA and ASIC platforms.

Figures (8)

• Figure 1: RTL Block Diagram of the LIF Neuron Core. The design utilizes a centralized accumulator and specialized registers for weights, decay, and threshold comparison.
• Figure 2: Poisson Encoder Block diagram
• Figure 3: Block diagram of the proposed Leaky Integrate-and-Fire (LIF) Neuron Array architecture. The centralized Controller manages enable signals (e$n_0$ to e$n_9$) for sequential neuron processing. Spikes generated by the LIF neurons are aggregated in the Spike Register and fed back to the controller for dynamic regulation.
• Figure 4: Membrane potential evolution over time. The neuron integrates input spikes, fires when crossing the threshold (red line), and resets.
• Figure 5: Classification accuracy vs. Simulation Timesteps. The network converges to $\sim$89% accuracy within 10 cycles.