Domain-specific Hardware Acceleration for Model Predictive Path Integral Control

TL;DR

This paper tackles real-time trajectory optimization for nonlinear robotic systems by focusing on Model Predictive Path Integral (MPPI) control, a sampling-based variant of MPC. It introduces a dedicated hardware accelerator, implemented on FPGA, to pipeline and parallelize the rollout step of MPPI, aiming to outperform GPU-based implementations in throughput and energy efficiency. Simulations with a quadrotor demonstrate that the pipelined accelerator yields smoother trajectories and better obstacle avoidance, even with fewer parallel rollouts. Synthesis results on an Alveo FPGA highlight resource tradeoffs and motivate future work toward ASIC implementations and full MPPI acceleration.

Abstract

Accurately controlling a robotic system in real time is a challenging problem. To address this, the robotics community has adopted various algorithms, such as Model Predictive Control (MPC) and Model Predictive Path Integral (MPPI) control. The first is difficult to implement on non-linear systems such as unmanned aerial vehicles, whilst the second requires a heavy computational load. GPUs have been successfully used to accelerate MPPI implementations; however, their power consumption is often excessive for autonomous or unmanned targets, especially when battery-powered. On the other hand, custom designs, often implemented on FPGAs, have been proposed to accelerate robotic algorithms while consuming considerably less energy than their GPU (or CPU) implementation. However, no MPPI custom accelerator has been proposed so far. In this work, we present a hardware accelerator for MPPI control and simulate its execution. Results show that the MPPI custom accelerator allows more accurate trajectories than GPU-based MPPI implementations.

Figures (6)

• Figure 1: Architecture of the proposed accelerator.
• Figure 2: Example of a three stage pipeline applied to the sequence $(\alpha_0, \beta_0, \gamma_0)$
• Figure 3: Simulation without obstacles. Position is plotted in 3D space. Above, the simulated system contains a GPU executing 2000 parallel rollouts, whilst at the bottom the system is simulated as if it had a FPGA with 200 parallel pipelines.
• Figure 4: Simulation without an obstacle. On the left, the simulated system contains a GPU executing 2000 parallel rollouts, whilst on the right the system is simulated as if it had a FPGA with 200 parallel pipelines. The first row contains position plotted against time, and the second row presents the inputs (i.e. commands sent to the actuators), also plotted against time.
• Figure 5: Simulation with an obstacle. Position is plotted in 3D space; the red box is an obstacle. Above, the simulated system contains a GPU executing 2000 parallel rollouts, whilst at the bottom the system is simulated as if it had a FPGA with 200 parallel pipelines.