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IMS: Intelligent Hardware Monitoring System for Secure SoCs

Wadid Foudhaili, Aykut Rencber, Anouar Nechi, Rainer Buchty, Mladen Berekovic, Andres Gomez, Saleh Mulhem

TL;DR

This work addresses AXI protocol-level denial-of-service vulnerabilities in SoCs by introducing the Intelligent Hardware Monitoring System (IMS), a hardware-accelerated, ML-based monitor that detects real-time protocol violations on AXI interconnects. IMS is developed end-to-end—from dataset generation with synthesized DoS attacks, through feature engineering and a quantized ML model, to RTL generation and FPGA deployment on a RISC-V SoC using HLS4ML. The approach achieves near-perfect detection with AUC-ROC ≈ 0.99 and high recall, while incurring minimal hardware overhead on a ZCU104 FPGA (0.23% DSP, 0.70% FF, 9.04% LUT) and a latency of about 1.57 ms, enabling >2.5 million inferences per second. A public AXI-traffic dataset and strong attack-specific results demonstrate IMS’s practicality for securing on-chip interconnects in edge environments and its potential for ASIC integration in the future.

Abstract

In the modern Systems-on-Chip (SoC), the Advanced eXtensible Interface (AXI) protocol exhibits security vulnerabilities, enabling partial or complete denial-of-service (DoS) through protocol-violation attacks. The recent countermeasures lack a dedicated real-time protocol semantic analysis and evade protocol compliance checks. This paper tackles this AXI vulnerability issue and presents an intelligent hardware monitoring system (IMS) for real-time detection of AXI protocol violations. IMS is a hardware module leveraging neural networks to achieve high detection accuracy. For model training, we perform DoS attacks through header-field manipulation and systematic malicious operations, while recording AXI transactions to build a training dataset. We then deploy a quantization-optimized neural network, achieving 98.7% detection accuracy with <=3% latency overhead, and throughput of >2.5 million inferences/s. We subsequently integrate this IMS into a RISC-V SoC as a memory-mapped IP core to monitor its AXI bus. For demonstration and initial assessment for later ASIC integration, we implemented this IMS on an AMD Zynq UltraScale+ MPSoC ZCU104 board, showing an overall small hardware footprint (9.04% look-up-tables (LUTs), 0.23% DSP slices, and 0.70% flip-flops) and negligible impact on the overall design's achievable frequency. This demonstrates the feasibility of lightweight, security monitoring for resource-constrained edge environments.

IMS: Intelligent Hardware Monitoring System for Secure SoCs

TL;DR

This work addresses AXI protocol-level denial-of-service vulnerabilities in SoCs by introducing the Intelligent Hardware Monitoring System (IMS), a hardware-accelerated, ML-based monitor that detects real-time protocol violations on AXI interconnects. IMS is developed end-to-end—from dataset generation with synthesized DoS attacks, through feature engineering and a quantized ML model, to RTL generation and FPGA deployment on a RISC-V SoC using HLS4ML. The approach achieves near-perfect detection with AUC-ROC ≈ 0.99 and high recall, while incurring minimal hardware overhead on a ZCU104 FPGA (0.23% DSP, 0.70% FF, 9.04% LUT) and a latency of about 1.57 ms, enabling >2.5 million inferences per second. A public AXI-traffic dataset and strong attack-specific results demonstrate IMS’s practicality for securing on-chip interconnects in edge environments and its potential for ASIC integration in the future.

Abstract

In the modern Systems-on-Chip (SoC), the Advanced eXtensible Interface (AXI) protocol exhibits security vulnerabilities, enabling partial or complete denial-of-service (DoS) through protocol-violation attacks. The recent countermeasures lack a dedicated real-time protocol semantic analysis and evade protocol compliance checks. This paper tackles this AXI vulnerability issue and presents an intelligent hardware monitoring system (IMS) for real-time detection of AXI protocol violations. IMS is a hardware module leveraging neural networks to achieve high detection accuracy. For model training, we perform DoS attacks through header-field manipulation and systematic malicious operations, while recording AXI transactions to build a training dataset. We then deploy a quantization-optimized neural network, achieving 98.7% detection accuracy with <=3% latency overhead, and throughput of >2.5 million inferences/s. We subsequently integrate this IMS into a RISC-V SoC as a memory-mapped IP core to monitor its AXI bus. For demonstration and initial assessment for later ASIC integration, we implemented this IMS on an AMD Zynq UltraScale+ MPSoC ZCU104 board, showing an overall small hardware footprint (9.04% look-up-tables (LUTs), 0.23% DSP slices, and 0.70% flip-flops) and negligible impact on the overall design's achievable frequency. This demonstrates the feasibility of lightweight, security monitoring for resource-constrained edge environments.
Paper Structure (19 sections, 3 figures, 7 tables)

This paper contains 19 sections, 3 figures, 7 tables.

Table of Contents

  1. Introduction
  2. SoC Denial of Service
  3. Paper Contributions
  4. Background & Motivation
  5. Threat Model
  6. Hardware-Based Security Monitoring
  7. Research Gap and Motivation
  8. IMS Design Methodology and Realization
  9. IMS Design Steps
  10. Dataset construction and Attack Synthesis
  11. Pre-processing Pipeline and Feature Engineering
  12. ML Model Architecture and Training
  13. Hardware Implementation, Optimization and Discussion
  14. IMS Implementation and Optimization
  15. IMS Detectability Analysis
  16. ...and 4 more sections

Figures (3)

  • Figure 1: AXI-Bus Hardware Monitoring System Concept
  • Figure 2: Overview of the IMS Design Steps
  • Figure 3: AXI Protocol Example of Security Vulnerabilities and Attacks Vectors