InterPUF: Distributed Authentication via Physically Unclonable Functions and Multi-party Computation for Reconfigurable Interposers

TL;DR

InterPUF addresses the trust gap in heterogeneous SiP with reconfigurable interposers by embedding a route-based differential delay PUF directly in the interposer and securing authentication with two-party MPC to prevent exposure of raw PUF data. The architecture yields a fixed SiP-wide root of trust with negligible area (<0.23%), minuscule per-chiplet overhead, and sub- tens of nanoseconds interposer authentication latency, followed by lightweight chiplet verification. Open-source RTL and simulation results demonstrate strong PUF quality (uniformity ≈0.5, reliability ≈98%), robust resistance to modeling and replay attacks, and scalability to large chiplet counts. Overall, InterPUF offers a practical, minimal-trust security primitive for plug-and-play chiplet ecosystems, enabling secure heterogeneous integration at scale.

Abstract

Modern system-in-package (SiP) platforms increasingly adopt reconfigurable interposers to enable plug-and-play chiplet integration across heterogeneous multi-vendor ecosystems. However, this flexibility introduces severe trust challenges, as traditional authentication schemes fail to scale or adapt in decentralized, post-fabrication programmable environments. This paper presents InterPUF, a compact and scalable authentication framework that transforms the interposer into a distributed root of trust. InterPUF embeds a route-based differential delay physically unclonable function (PUF) across the reconfigurable interconnect and secures authentication using multi-party computation (MPC), ensuring raw PUF signatures are never exposed. Our hardware evaluation shows only 0.23% area and 0.072% power overhead across diverse chiplets while preserving authentication latency within tens of nanoseconds. Simulation results using pyPUF confirm strong uniqueness, reliability, and modeling resistance under process, voltage, and temperature variations. By combining interposer-resident PUF primitives with cryptographic hashing and collaborative verification, InterPUF enforces a minimal-trust authentication model without relying on a centralized anchor.

Figures (7)

• Figure 1: Comparison of development time across design flows. Each bar illustrates the sequence and duration of design stages. As it evolves from full-custom to chiplet-based integration, redundant steps e.g., Register Transfer Level (RTL) design or physical implementation are reduced or eliminated, shortening time-to-market.
• Figure 2: SiP design flow and life-cycle. Untrusted and trusted parties are marked by red and green boxes, respectively.
• Figure 3: Architecture of InterPUF. (a) Physical organization of the system, where the bottom layer integrates the interconnect mesh with embedded $N$-stage crossbar chains and differential arbiters, and the top layer hosts chiplets interconnected through the fabric. (b) Authentication controller, which manages challenge hashing, scheduling, differential arbitration, majority/reliability voting, and response hashing.
• Figure 4: Operation flow of InterPUF.
• Figure 5: Waveform diagram of authentication stages in InterPUF. The interconnect PUF completes in $6$ cycles and can be repeated multiple times within a single SHA-256 window ($96$ cycles). This ensures that interconnect validation is established as the root of trust before authentication.