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RidgeWalker: Perfectly Pipelined Graph Random Walks on FPGAs

Hongshi Tan, Yao Chen, Xinyu Chen, Qizhen Zhang, Cheng Chen, Weng-Fai Wong, Bingsheng He

TL;DR

RidgeWalker addresses the bottlenecks of accelerating graph random walks (GRWs) on hardware by exploiting the Markov property to decompose each hop into stateless tasks that can be executed out-of-order. It fuses asynchronous pipelines with a queuing-theory–based zero-bubble scheduler to realize perfect pipelining, sustaining high utilization even under irregular GRW workloads and memory-latency. The architecture saturates random-access bandwidth through an asynchronous memory engine and a modular N-to-N balancer/dispatcher/merger, achieving up to $71.0\times$ FPGA and $22.9\times$ GPU speedups across multiple GRW algorithms on real and synthetic graphs. RidgeWalker demonstrates broad applicability to PPR, URW, DeepWalk, Node2Vec, and MetaPath, offering a scalable path toward high-performance GRW accelerators for datacenter workloads.

Abstract

Graph Random Walks (GRWs) offer efficient approximations of key graph properties and have been widely adopted in many applications. However, GRW workloads are notoriously difficult to accelerate due to their strong data dependencies, irregular memory access patterns, and imbalanced execution behavior. While recent work explores FPGA-based accelerators for GRWs, existing solutions fall far short of hardware potential due to inefficient pipelining and static scheduling. This paper presents RidgeWalker, a high-performance GRW accelerator designed for datacenter FPGAs. The key insight behind RidgeWalker is that the Markov property of GRWs allows decomposition into stateless, fine-grained tasks that can be executed out-of-order without compromising correctness. Building on this, RidgeWalker introduces an asynchronous pipeline architecture with a feedback-driven scheduler grounded in queuing theory, enabling perfect pipelining and adaptive load balancing. We prototype RidgeWalker on datacenter FPGAs and evaluated it across a range of GRW algorithms and real-world graph datasets. Experimental results demonstrate that RidgeWalker achieves an average speedup of 7.0x over state-of-the-art FPGA solutions and 8.1x over GPU solutions, with peak speedups of up to 71.0x and 22.9x, respectively. The source code is publicly available at https://github.com/Xtra-Computing/RidgeWalker.

RidgeWalker: Perfectly Pipelined Graph Random Walks on FPGAs

TL;DR

RidgeWalker addresses the bottlenecks of accelerating graph random walks (GRWs) on hardware by exploiting the Markov property to decompose each hop into stateless tasks that can be executed out-of-order. It fuses asynchronous pipelines with a queuing-theory–based zero-bubble scheduler to realize perfect pipelining, sustaining high utilization even under irregular GRW workloads and memory-latency. The architecture saturates random-access bandwidth through an asynchronous memory engine and a modular N-to-N balancer/dispatcher/merger, achieving up to FPGA and GPU speedups across multiple GRW algorithms on real and synthetic graphs. RidgeWalker demonstrates broad applicability to PPR, URW, DeepWalk, Node2Vec, and MetaPath, offering a scalable path toward high-performance GRW accelerators for datacenter workloads.

Abstract

Graph Random Walks (GRWs) offer efficient approximations of key graph properties and have been widely adopted in many applications. However, GRW workloads are notoriously difficult to accelerate due to their strong data dependencies, irregular memory access patterns, and imbalanced execution behavior. While recent work explores FPGA-based accelerators for GRWs, existing solutions fall far short of hardware potential due to inefficient pipelining and static scheduling. This paper presents RidgeWalker, a high-performance GRW accelerator designed for datacenter FPGAs. The key insight behind RidgeWalker is that the Markov property of GRWs allows decomposition into stateless, fine-grained tasks that can be executed out-of-order without compromising correctness. Building on this, RidgeWalker introduces an asynchronous pipeline architecture with a feedback-driven scheduler grounded in queuing theory, enabling perfect pipelining and adaptive load balancing. We prototype RidgeWalker on datacenter FPGAs and evaluated it across a range of GRW algorithms and real-world graph datasets. Experimental results demonstrate that RidgeWalker achieves an average speedup of 7.0x over state-of-the-art FPGA solutions and 8.1x over GPU solutions, with peak speedups of up to 71.0x and 22.9x, respectively. The source code is publicly available at https://github.com/Xtra-Computing/RidgeWalker.
Paper Structure (39 sections, 1 theorem, 2 equations, 11 figures, 4 tables, 3 algorithms)

This paper contains 39 sections, 1 theorem, 2 equations, 11 figures, 4 tables, 3 algorithms.

Table of Contents

  1. Introduction
  2. Background
  3. CSR Graph Representation
  4. GRW Execution Flow
  5. Motivation and Design Principles
  6. The Need for Specialized Accelerators for GRWs
  7. Inefficiencies in Existing GRW Accelerators
  8. RidgeWalker: Towards Perfectly Pipelined GRWs
  9. RidgeWalker Overview
  10. Architecture Overview
  11. Query Execution Flow
  12. Out-of-order Concurrent Query Execution
  13. Decomposing Queries to Stateless Tasks
  14. Asynchronous Memory Access for Concurrent Execution
  15. Dynamic Query Reassignment Over Parallel Pipelines
  16. ...and 24 more sections

Key Result

Theorem 6.1

Consider a system with $N$ independent servers processing tasks, and each server is capable of processing up to $\mu$ tasks per cycle. Tasks are scheduled from a queue by a scheduler that receives feedback about server availability with a maximum delay of $C_\text{max}$ time. To ensure that all serv

Figures (11)

  • Figure 1: Illustration of the inherent randomness and imbalanced traversal in GRWs.
  • Figure 2: An example of graph representation in CSR format.
  • Figure 3: (a) Bandwidth analysis of SOTA FPGA accelerator FastRW gao2023fastrw, highlighting underutilization. (b) Perfectly pipelined parallel GRW execution on two pipelines, $Q_{sy}^x$ denotes the $y$-th step of traversal for query $x$.
  • Figure 4: RidgeWalker architecture overview.
  • Figure 5: Markov-based task decomposition and illustration of out-of-order query execution across two pipelines.
  • ...and 6 more figures

Theorems & Definitions (1)

  • Theorem 6.1: Minimum Buffer Queue Depth