Towards Tensor Network Models for Low-Latency Jet Tagging on FPGAs
Alberto Coppi, Ema Puljak, Lorenzo Borella, Daniel Jaschke, Enrique Rico, Maurizio Pierini, Jacopo Pazzini, Andrea Triossi, Simone Montangero
TL;DR
This paper investigates real-time jet tagging at HL-LHC Level-1 trigger using Tensor Network models (MPS and TTN) implemented on FPGAs for ultra-low-latency inference. It introduces physics-informed per-particle embeddings and employs quantum mutual information to optimize feature layout, achieving competitive full-precision performance across jet constituents. Through post-training quantization studies and FPGA synthesis, the work demonstrates sub-microsecond latency and manageable hardware resources, showing TNs as viable, interpretable alternatives to deep networks for trigger-level inference. The results support broader deployment of TN-based architectures in low-latency, resource-constrained environments and outline directions for further compression and gauge-aware quantization.
Abstract
We present a systematic study of Tensor Network (TN) models $\unicode{x2013}$ Matrix Product States (MPS) and Tree Tensor Networks (TTN) $\unicode{x2013}$ for real-time jet tagging in high-energy physics, with a focus on low-latency deployment on Field Programmable Gate Arrays (FPGAs). Motivated by the strict requirements of the HL-LHC Level-1 trigger system, we explore TNs as compact and interpretable alternatives to deep neural networks. Using low-level jet constituent features, our models achieve competitive performance compared to state-of-the-art deep learning classifiers. We investigate post-training quantization to enable hardware-efficient implementations without degrading classification performance or latency. The best-performing models are synthesized to estimate FPGA resource usage, latency, and memory occupancy, demonstrating sub-microsecond latency and supporting the feasibility of online deployment in real-time trigger systems. Overall, this study highlights the potential of TN-based models for fast and resource-efficient inference in low-latency environments.
