Bridging Superconducting and Neutral-Atom Platforms for Efficient Fault-Tolerant Quantum Architectures

TL;DR

The paper tackles the FTQC bottlenecks by proposing heterogeneous quantum architectures that marry fast SC gates with scalable NA connectivity. It introduces two concrete design strategies, MagicAcc (offloading magic-state factories to SC) and Memory–Compute Separation (allocating NA qLDPC memory and SC compute), under a unified HQ-ISA and cost-modeling framework. Through end-to-end analysis and design-space exploration, it shows substantial improvements in time (up to around 752× speedup) and spatial efficiency (up to ~10× footprint reduction) compared with homogeneous baselines, highlighting the pivotal role of interconnects, magic-state logistics, and memory organization. The work provides design principles and quantitative insights that guide application-to-architecture mapping for future fault-tolerant quantum computers, while acknowledging that further full-stack integration is needed for comprehensive optimization.

Abstract

The transition to the fault-tolerant era exposes the limitations of homogeneous quantum systems, where no single qubit modality simultaneously offers optimal operation speed, connectivity, and scalability. In this work, we propose a strategic approach to Heterogeneous Quantum Architectures (HQA) that synthesizes the distinct advantages of the superconducting (SC) and neutral atom (NA) platforms. We explore two architectural role assignment strategies based on hardware characteristics: (1) We offload the latency-critical Magic State Factory (MSF) to fast SC devices while performing computation on scalable NA arrays, a design we term MagicAcc, which effectively mitigates the resource-preparation bottleneck. (2) We explore a Memory-Compute Separation (MCSep) paradigm that utilizes NA arrays for high-density qLDPC memory storage and SC devices for fast surface-code processing. Our evaluation, based on a comprehensive end-to-end cost model, demonstrates that principled heterogeneity yields significant performance gains. Specifically, our designs achieve $752\times$ speedup over NA-only baselines on average and reduce the physical qubit footprint by over $10\times$ compared to SC-only systems. These results chart a clear pathway for leveraging cross-modality interconnects to optimize the space-time efficiency of future fault-tolerant quantum computers.

Figures (7)

• Figure 1: Overview of proposed heterogeneous quantum architectures and the derived design space.
• Figure 2: Background on FTQC. (a) GBC and PBC layers. (b) Logical operation on surface codes (transversal gates vs. lattice surgery). (c) Realizing non-Clifford operations by consuming the magic state $|T\rangle = (|0\rangle+e^{i\frac{\pi}{4}}|1\rangle)/\sqrt{2}$).
• Figure 3: Compute modeling for GBC and PBC schemes.
• Figure 4: Modeling of store/load overhead due to limited compute and buffer size.
• Figure 5: Architecture analysis for (a) MAcc speedup and (b) MCSep space-time trade-off.