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Interfacing Superconductor and Semiconductor Digital Electronics

Yerzhan Mustafa, Selçuk Köse

TL;DR

This survey investigates the challenge of interfacing superconducting SFQ-based digital electronics with semiconductor CMOS logic. It analyzes a taxonomy of interface circuits, focusing on JJ-based output drivers and multi-terminal devices, and evaluates their performance in terms of data rate, output voltage, power, layout, biasing, flux trapping, BER, and hardware security. The study highlights a fundamental trade-off: no single driver simultaneously delivers high voltage and high data rate, guiding design choices for applications in HPC, superconducting quantum computing, DSP, and beyond. It also discusses fabrication technologies, the role of semiconductor amplifiers, and promising directions such as ferromagnetic JJs, bistable elements, and advanced HTS processes for future scalable hybrid systems.

Abstract

Interface circuits are the key components that enable the hybrid integration of superconductor and semiconductor digital electronics. The design requirements of superconductor-semiconductor interface circuits vary depending on the application, such as high-performance classical computing, superconducting quantum computing, and digital signal processing. In this survey, various interface circuits are categorized based on the working principle and structure. The superconducting output drivers are explored, which are capable of converting and amplifying, e.g., single flux quantum (SFQ) voltage pulses, to voltage levels that semiconductor circuits can process. Several trade-offs between circuit- and system-level design parameters are examined. Accordingly, parameters such as the data rate, output voltage, power dissipation, layout area, thermal/heat load of cryogenic cables, and bit-error rate are considered.

Interfacing Superconductor and Semiconductor Digital Electronics

TL;DR

This survey investigates the challenge of interfacing superconducting SFQ-based digital electronics with semiconductor CMOS logic. It analyzes a taxonomy of interface circuits, focusing on JJ-based output drivers and multi-terminal devices, and evaluates their performance in terms of data rate, output voltage, power, layout, biasing, flux trapping, BER, and hardware security. The study highlights a fundamental trade-off: no single driver simultaneously delivers high voltage and high data rate, guiding design choices for applications in HPC, superconducting quantum computing, DSP, and beyond. It also discusses fabrication technologies, the role of semiconductor amplifiers, and promising directions such as ferromagnetic JJs, bistable elements, and advanced HTS processes for future scalable hybrid systems.

Abstract

Interface circuits are the key components that enable the hybrid integration of superconductor and semiconductor digital electronics. The design requirements of superconductor-semiconductor interface circuits vary depending on the application, such as high-performance classical computing, superconducting quantum computing, and digital signal processing. In this survey, various interface circuits are categorized based on the working principle and structure. The superconducting output drivers are explored, which are capable of converting and amplifying, e.g., single flux quantum (SFQ) voltage pulses, to voltage levels that semiconductor circuits can process. Several trade-offs between circuit- and system-level design parameters are examined. Accordingly, parameters such as the data rate, output voltage, power dissipation, layout area, thermal/heat load of cryogenic cables, and bit-error rate are considered.
Paper Structure (20 sections, 5 figures)

This paper contains 20 sections, 5 figures.

Table of Contents

  1. Introduction
  2. The Need for Superconductor-Semiconductor Interface Circuits
  3. Taxonomy of Superconductor-Semiconductor Interface Circuits
  4. JJ-based output drivers
  5. Latching drivers
  6. SQUID-based drivers
  7. Multi-terminal devices
  8. Cryotron
  9. Superconductor-based transistor
  10. Effect of Fabrication Technology
  11. JJ-based output drivers
  12. Semiconductor amplifiers
  13. Comparison of Superconducting Output Drivers
  14. Circuit-level parameters
  15. Heat load of cryogenic cables
  16. ...and 5 more sections

Figures (5)

  • Figure 1: a, Block diagram of the cryostat with superconductor, semiconductor, photonic, and quantum chips. The superconductor-semiconductor interface circuits are highlighted in green boxes. Digital output data links are shown with green arrows. b, Taxonomy of the superconducting output drivers.
  • Figure 2: Schematics of JJ-based output drivers. a, SQUID stack with RSFFs hashimoto2007implementation. The inset shows the schematic of DC SQUID cell. b, HUFFLE driver hebard1979dc. c, SFQ-to-DC converter based on TFF likharev1991rsfqsupertools_rsfq_cell_library. d, Suzuki stack with 16-JJ configuration ortlepp2013design. e, Voltage doubler ortlepp2009superconductor. f, 4JL gate konno2017fully. Shunt resistors and parasitic inductances of JJs are not shown. A novel symbol of JJ is used that is standardized by International Electrotechnical Commission new_JJ_symbol.
  • Figure 3: Simulation of JJ-based output drivers. Simulated in JoSIM delport2019josim using MIT Lincoln Lab SFQ5ee process with the critical current density of 100 µ A/µ m$^2$tolpygo2016advanced. a, 16-stage SQUID stack with RSFFs, b, SFQ-to-DC converter, and c, voltage doubler are operating at 20 Gbps with 50 $\Omega$ and 100 pH load. The input signal of voltage doubler is modeled as a 100 GHz SFQ pulse train ortlepp2009superconductor. d, HUFFLE driver operating at 2 Gbps with $L_{out}$ = 100 pH. e, 16-JJ Suzuki stack is operating at 5 Gbps with 50 $\Omega$, 100 pH, and 180 fF load. f, 4JL gate circuit is operating at 5 Gbps with 50 $\Omega$ and 100 pH load. The circuit parameters are similar to designs presented in mustafa2025spamsupertools_rsfq_cell_librarykaplunenko1991singlehebard1979dcortlepp2013designkonno2017fully.
  • Figure 4: Multi-terminal devices. Layout view/structure of a, nanocryotron (nTron) mccaughan2014superconducting, b, multi-layered heater-cryotron (hTron) baghdadi2020multilayered, c, nanowire meander switch mccaughan2019superconducting, and d, wire-based cryotron (wTron) paul2025photolithography. The circuit symbols of e, nTron, f, multi-layered hTron, g, nanowire meander switch, and h, wTron.
  • Figure 5: Comparison of superconducting output drivers. a, Output voltage and data rate parameters comparison. b, General trends in output voltage, data rate, power dissipation, layout area, and bias type. Green, orange, and red colors ($\bigtriangleup$, $\Diamond$, and $\bigtriangledown$ symbols) correspond to desired, intermediate, and undesired performance, respectively. c, FOM and layout area parameters comparison. d, FOM and output voltage parameters comparison. FOM is calculated as power dissipation (only circuit-level component) divided by data rate.