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Time-Dynamic Circuits for Fault-Tolerant Shift Automorphisms in Quantum LDPC Codes

Younghun Kim, Spiro Gicev, Martin Sevior, Muhammad Usman

TL;DR

The paper addresses the challenge of implementing fault-tolerant shift automorphisms in qLDPC codes, where SWAP-based approaches incur large logical error rates and time overhead. It introduces time-dynamic syndrome extraction circuits that realize shift automorphisms during syndrome measurements, preserving circuit distance. Through benchmarks on weight-6 generalized toric codes (including twisted/untwisted and the gross code), the authors show shift circuits dramatically reduce logical error rates compared with SWAP-based methods and approach the performance of idle memory, with a measured ~$38$-fold improvement at $p=10^{-3}$ for the gross code and a near-memory-like performance with a ratio of about $1.7$. The work highlights a practical path toward implementing logical Pauli measurements in qLDPC architectures and paves the way for leakage-removal schemes and broader adoption beyond surface codes, with potential decoder and hardware adaptations to further optimize performance.

Abstract

Quantum low-density parity-check (qLDPC) codes have emerged as a promising approach for realizing low-overhead logical quantum memories. Recent theoretical developments have established shift automorphisms as a fundamental building block for completing the universal set of logical gates for qLDPC codes. However, practical challenges remain because the existing SWAP-based shift automorphism yields logical error rates that are orders of magnitude higher than those for fault-tolerant idle operations. In this work, we address this issue by dynamically varying the syndrome measurement circuits to implement the shift automorphisms without reducing the circuit distance. We benchmark our approach on both twisted and untwisted weight-6 generalized toric codes, including the gross code family. Our time-dynamic circuits for shift automorphisms achieve performance comparable to the idle operations under the circuit-level noise model (SI1000). Specifically, the dynamic circuits achieve more than an order of magnitude reduction in logical error rates relative to the SWAP-based scheme for the gross code at a physical error rate of $10^{-3}$, employing the BP-OSD decoder. Our findings improve both the error resilience and the time overhead of the shift automorphisms in qLDPC codes. Furthermore, our work can lead to alternative syndrome extraction circuit designs, such as leakage removal protocols, providing a practical pathway to utilizing dynamic circuits that extend beyond surface codes towards qLDPC codes.

Time-Dynamic Circuits for Fault-Tolerant Shift Automorphisms in Quantum LDPC Codes

TL;DR

The paper addresses the challenge of implementing fault-tolerant shift automorphisms in qLDPC codes, where SWAP-based approaches incur large logical error rates and time overhead. It introduces time-dynamic syndrome extraction circuits that realize shift automorphisms during syndrome measurements, preserving circuit distance. Through benchmarks on weight-6 generalized toric codes (including twisted/untwisted and the gross code), the authors show shift circuits dramatically reduce logical error rates compared with SWAP-based methods and approach the performance of idle memory, with a measured ~-fold improvement at for the gross code and a near-memory-like performance with a ratio of about . The work highlights a practical path toward implementing logical Pauli measurements in qLDPC architectures and paves the way for leakage-removal schemes and broader adoption beyond surface codes, with potential decoder and hardware adaptations to further optimize performance.

Abstract

Quantum low-density parity-check (qLDPC) codes have emerged as a promising approach for realizing low-overhead logical quantum memories. Recent theoretical developments have established shift automorphisms as a fundamental building block for completing the universal set of logical gates for qLDPC codes. However, practical challenges remain because the existing SWAP-based shift automorphism yields logical error rates that are orders of magnitude higher than those for fault-tolerant idle operations. In this work, we address this issue by dynamically varying the syndrome measurement circuits to implement the shift automorphisms without reducing the circuit distance. We benchmark our approach on both twisted and untwisted weight-6 generalized toric codes, including the gross code family. Our time-dynamic circuits for shift automorphisms achieve performance comparable to the idle operations under the circuit-level noise model (SI1000). Specifically, the dynamic circuits achieve more than an order of magnitude reduction in logical error rates relative to the SWAP-based scheme for the gross code at a physical error rate of , employing the BP-OSD decoder. Our findings improve both the error resilience and the time overhead of the shift automorphisms in qLDPC codes. Furthermore, our work can lead to alternative syndrome extraction circuit designs, such as leakage removal protocols, providing a practical pathway to utilizing dynamic circuits that extend beyond surface codes towards qLDPC codes.
Paper Structure (12 sections, 11 equations, 8 figures, 7 tables)

This paper contains 12 sections, 11 equations, 8 figures, 7 tables.

Figures (8)

  • Figure 1: Toric layout of a weight-6 generalized toric code. (a) Each unit cell of the code comprises two types of check operators (X and Z) and two types of data qubits (R and L), represented by distinct colors. (b) The full layout forms an $\ell\times m$ grid assembled from these unit cells, with each cell assigned coordinates defined by a polynomial representation. The CNOT gates illustrate interactions between the R and L data qubits and their corresponding X and Z check operators. The depicted layout corresponds to the gross code family, where the parameter determines the geometric nonlocality of the check operators set $(a,b,c,d)=(-1,3,3,-1)$. (c) Each unit cell moves under the basic shift automorphisms $s=x$ and $s=y$. The diagrams illustrate the physical qubit permutations that are equivalent to the basic shift automorphisms; these operations rearrange the lattice (black arrows), effectively shifting the unit cell coordinates according to the mappings $x^i y^j \xmapsto{s=x} x^{i+1} y^j$ and $x^i y^j \xmapsto{s=y} x^i y^{j+1}$.
  • Figure 2: Shift circuits for implementing shift automorphisms. (a) Two SWAP layers are inserted between the former and latter syndrome extraction cycles (SEC). The former SEC ends with CNOT gates aligned with the first SWAP layer, while the latter SEC begins with CNOT gates corresponding to the same qubit pairs as the second SWAP layer. The red dotted arrows represent where each SWAP layer is absorbed to construct a shift circuit. (b) By decomposing the SWAP gates into CNOT gates, redundant operations are canceled, effectively reducing the circuit depth. The decomposition results in a single additional layer of two-qubit gates in the former SEC and replaces syndrome qubit measurements with data qubit measurements, while simultaneously reversing the roles of control and target qubits in the initial CNOT gates of the subsequent SEC.
  • Figure 3: SWAP gate decomposition. A SWAP gate can be decomposed into three CNOT gates.
  • Figure 4: Logical error rates and failure spectrum fitting of the gross code family. The logical performance of three logical instructions, Shift circuit (green), SWAP-based shift automorphisms (blue), and Memory (black), is evaluated for the $[[72,12,6]]$ code (top) and the gross code $[[144,12,12]]$ (bottom) using the BP-OSD decoder under the SI1000 noise model. The circuit distances for the two codes are estimated to be $d_{circ}=6$ and $d_{circ}=10$, following Ref. yoder_tour_2025, respectively. For each circuit, the logical error rate $p_L$ is plotted as a function of the physical error rate $p$, with data points obtained via Monte Carlo sampling and dotted lines representing the failure spectrum. Uncertainties of data points are calculated assuming binomial statistics for a $99\%$ confidence interval using sintergidney_stim_2021. Details of the fitted parameters of the failure spectrum are provided in Table \ref{['tab:fit_params']}.
  • Figure 5: Logical error rates and failure spectrum fitting of the twisted toric codes. The logical performance of three logical instructions, Shift circuit (green), SWAP-based shift automorphisms (blue), and Memory (black), is evaluated for the twisted toric codes, the $[[120,8,12]]$ code (top) and the $[[170,16,10]]$ code (bottom), using the BP-OSD decoder under the SI1000 noise model. The circuit distances for the two codes are estimated to be $d_{circ}=10$ for both codes, following Ref. yoder_tour_2025. For each circuit, the logical error rate $p_L$ is plotted as a function of the physical error rate $p$, with data points obtained via Monte Carlo sampling and dotted lines representing the failure spectrum. Uncertainties of data points are calculated assuming binomial statistics for a $99\%$ confidence interval using sintergidney_stim_2021.
  • ...and 3 more figures