Forward-only learning in memristor arrays with month-scale stability

TL;DR

This work tackles the challenge of on-chip learning in memristor arrays, where conventional high-energy, multi-pulse programming and backward signal flow hinder practicality. It demonstrates sub-1 V reset-only updates on standard filamentary HfOx/Ti memristors and adopts forward-only learning via Forward-Forward approaches, specifically supervised Forward-Forward (SFF) and competitive forward (CF), to avoid backpropagation. On a bear-classification transfer task using up to 8,064 devices, SFF and CF achieve test accuracies of 89.5% and 89.6% respectively, closely matching a 90.0% backpropagation reference, with consistency across runs. The trained models retain accuracy for at least one month under ambient conditions, illustrating month-scale stability and endurance advantages, while energy analysis shows sub-1 V resets are ~460× more energy-efficient than program-and-verify and only ~46% above inference. Together, these results provide a practical, pulse-aware route to energy-efficient on-chip learning and adaptive edge intelligence in memristor arrays.

Abstract

Turning memristor arrays from efficient inference engines into systems capable of on-chip learning has proved difficult. Weight updates have a high energy cost and cause device wear, analog states drift, and backpropagation requires a backward pass with reversed signal flow. Here we experimentally demonstrate learning on standard filamentary HfOx/Ti arrays that addresses these challenges with two design choices. First, we realize that standard filamentary HfOx/Ti memristors support sub-1 V reset-only pulses that cut energy, improve endurance, and yield stable analog states. Second, we rely on forward-only training algorithms derived from Hinton's Forward-Forward that use only inference-style operations. We train two-layer classifiers on an ImageNet-resolution four-class task using arrays up to 8,064 devices. Two forward-only variants, the double-pass supervised Forward-Forward and a single-pass competitive rule, achieve test accuracies of 89.5% and 89.6%, respectively; a reference experiment using backpropagation reaches 90.0%. Across five independent runs per method, these accuracies match within statistical uncertainty. Trained models retain accuracy for at least one month under ambient conditions, consistent with the stability of reset-only states. Sub-1 V reset updates use 460 times less energy than conventional program-and-verify programming and require just 46% more energy than inference-only operation. Together, these results establish forward-only, sub-1 V learning on standard filamentary stacks at array scale, outlining a practical, pulse-aware route to adaptive edge intelligence.

Figures (4)

• Figure 1: Sub-1 V reset regime of HfO$_x$/Ti memristors.a Focused ion beam–scanning electron microscopy (FIB-SEM) image of a cut circuit showing memristor integrated over CMOS. b Proposed low-voltage reset procedure: No conductance is targeted, only its progressive decrease via the partial dissolution of an existing filament via repeated, same-low-voltage pulses. c To both increase and decrease weights, as well as enabling negative values, memristors are in pairs. The difference of their conductance is encoding a single weight and therefore only one of the two have a low-voltage pulse applied to depending on the sign of the update. d Endurance of four devices programmed with sub-1 V reset: for each device, the dynamics over 5,000 pulses stays similar after 300 cycles and 1,500,000 pulses. The curves are averaged over the 20 first and 20 last cycles. e Retention of 3,456 devices programmed with sub-1 V reset: 8 days after training, 94.1% drifted by less than 3 $\mu$S, and 90.7% after 90 days. f Distribution of the Pearson coefficient of conductance vs. pulse number curves for 1,268 memristors. Randomly-chosen examples of curves are presented for different Pearson coefficients.
• Figure 2: Experimental transfer training of a memristor crossbar on bear classification using perceptron architecture. a Topology of the trained architecture associating a ResNet pretrained on ImageNet with a memristor crossbar trained on bear species classification. b Focused ion beam–scanning electron microscopy (FIB-SEM) image of a memristor array integrated over CMOS. c Optical microscopy image of the multiply-and-accumulate (MAC) memristor/CMOS integrated circuit. d Experimental validation of the MAC functionality: measured output as a function of result expected from software MAC on a variety of inputs (see Methods). e Evolution of validation accuracy over five experimental realizations of the training. MAC operations as well as memristor updates are performed on-chip. f Comparison of the mean result of e with the mean results of five control experiments where only memristor updates are performed on-chip, and MACs are emulated by software to speed up experiments.
• Figure 3: Experimental transfer training of a memristor crossbar on bear classification using a multilayer perceptron architecture and backpropagation. a Topology of the trained architecture associating a ResNet pretrained on ImageNet with two memristor crossbars. b Optical microscopy image and simplified schematic of the "large array" memristor/CMOS integrated circuit. c Evolution of validation accuracy over five experimental realizations of the training. All memristor updates are performed on-chip, MACs are emulated by software to speed up experiments (unlike Fig. \ref{['fig:backprop1']} where they are performed on chip). d Evolution of the validation accuracy over time once training is finished for one circuit. e t-SNE representation of the bear test dataset. The samples initially classified correctly and then incorrectly after 8 and 20 days are marked.
• Figure 4: Experimental transfer training of a memristor crossbar on bear classification using forward-only training approaches. a Illustration of our Forward-Forward approach using "positive" and "negative" examples and a second memristor layer with competitive clusters. b Evolution of validation accuracy on bear classification over five experimental realizations of Forward-Forward training. Methodology for experiments is the same as Fig. \ref{['fig:backprop2']}. c Illustration of our competitive forward approach using two memristor layers with competitive clusters. d Evolution of validation accuracy on bear classification over five experimental realizations of competitive forward training. e Evolution of the validation accuracy over time once training is finished for one circuit trained with competitive forward. f Comparison of mean test accuracy, and mean number of sub-1 V reset pulses per device in our experiments employing backpropagation, Forward-Forward, and competitive forward training.