Geometry- and Topology-Informed Quantum Computing: From States to Real-Time Control with FPGA Prototypes

TL;DR

The book reframes quantum computing as a hardware-aware, geometry-informed real-time pipeline, integrating quantum state evolution with deterministic classical processing. It develops foundational geometry (Bloch sphere, differential geometry, QFIM) and then builds an FPGA-oriented real-time QEC infrastructure, followed by geometry-guided optimization and optional cryptographic streaming, all within an artifacts-driven workflow. Key contributions include a deployable Track A QEC decoder, geometry-based optimization via QFIM/QNG, and a rigorous artifact ladder (study→research→development) with concrete latency and benchmarking templates. This approach enables reliable, tail-aware control of hybrid quantum systems across platforms, bridging theory and RTL-level implementations for near-term and fault-tolerant regimes.

Abstract

This book gives a geometry-first, hardware-aware route through quantum-information workflows, with one goal: connect states, circuits, and measurement to deterministic classical pipelines that make hybrid quantum systems run. Part 1 develops the backbone (essential linear algebra, the Bloch-sphere viewpoint, differential-geometric intuition, and quantum Fisher information geometry) so evolution can be read as motion on curved spaces and measurement as statistics. Part 2 reframes circuits as dataflow graphs: measurement outcomes are parsed, aggregated, and reduced to small linear-algebra updates that schedule the next pulses, highlighting why low-latency, low-jitter streaming matters. Part 3 treats multi-qubit structure and entanglement as geometry and computation, including teleportation, superdense coding, entanglement detection, and Shor's algorithm via quantum phase estimation. Part 4 focuses on topological error correction and real-time decoding (Track A): stabilizer codes, surface-code decoding as "topology -> graph -> algorithm", and Union-Find decoders down to microarchitectural/RTL constraints, with verification, fault injection, and host/control-stack integration under product metrics (bounded latency, p99 tails, fail-closed policies, observability). Optional Track C covers quantum cryptography and streaming post-processing (BB84/E91, QBER/abort rules, privacy amplification, and zero-knowledge/post-quantum themes), emphasizing FSMs, counters, and hash pipelines. Appendices provide visualization-driven iCEstick labs (switch-to-bit conditioning, fixed-point phase arithmetic, FSM sequencing, minimal control ISAs), bridging principles to implementable systems.

Figures (106)

• Figure 1: State geometry for one qubit. Pure states live on the Bloch sphere (surface), while mixed states fill the Bloch ball (interior).
• Figure 2: A circuit $U(\theta)$ maps parameter updates into motion in state space. Geometry defines which motions are large (observable) or small (hard to learn).
• Figure 3: Topology-flavored picture: an error chain produces syndrome at its boundary endpoints. The decoder reconstructs a chain consistent with the observed boundary.
• Figure 4: Hybrid pipeline viewpoint: the QPU produces a measurement stream; FPGA computes bounded-latency decisions and drives the next control step.
• Figure 5: Eigenvectors define preferred axes: in the eigenbasis, a Hermitian matrix acts by stretching along orthogonal directions.

Theorems & Definitions (171)

• Definition 3.1: Bra-ket basics
• Example 3.2: Explicit outer product computation
• Definition 3.3: Rank-one projector
• proof : Idempotence in one line
• Definition 3.4: Standard inner product on $\mathbb{C}^n$
• Proposition 3.5: Cauchy--Schwarz
• Remark 3.6: Operational meaning
• Definition 3.7: Adjoint
• Definition 3.8: Unitary and Hermitian
• Proposition 3.9: Unitaries preserve norms and inner products