Sparse quantum state preparation with improved Toffoli cost

TL;DR

The paper tackles sparse quantum state preparation on $n$ qubits with $s$ nonzero amplitudes, a task whose fault-tolerant cost is dominated by Toffoli gates. It proposes a two-step approach: first prepare a dense state in a $\lceil\log(s)\rceil$-qubit subspace, then apply an isometry to map to the target sparse state, with a batched, batched unary-iteration-based isometry that replaces many multi-controlled-X gates. The main theoretical contribution is a tight worst-case Toffoli bound for the isometry, $\left\lceil \frac{s}{m} \right\rceil \left(2m + \frac{1}{2}\log\left(\frac{\tilde{s}}{m}\right) - 3\right) + \log\left(\frac{\tilde{s}^2}{m}\right)$, together with an ancilla budget of $\lceil\log(s)\rceil - 1$, where $m$ is the largest power of two not exceeding $n - \lceil\log(s)\rceil$ and $\tilde{s}=2^{\lceil\log(s)\rceil}$. The authors implement and analyze a classical algorithm to construct the isometry and demonstrate substantial empirical savings, including potential real-state optimizations, and discuss density-prep trade-offs via QROM/QROAM loading. Overall, the work provides the most resource-efficient sparse-state preparation circuits to date, with practical open-source tooling and clear pathways to further reductions in Toffoli cost for fault-tolerant quantum computing.

Abstract

The preparation of quantum states is one of the most fundamental tasks in quantum computing, and a key primitive in many quantum algorithms. Of particular interest to areas such as quantum simulation and linear-system solvers are sparse quantum states, which contain only a small number $s$ of non-zero computational basis states compared to a generic state. In this work, we present an approach that prepares $s$-sparse states on $n$ qubits, reducing the number of Toffoli gates required compared to prior art. We work in the established framework of first preparing a dense state on a $\lceil{\log(s)}\rceil$-qubit sub-register, and then mapping this state to the target state via an isometry, with the latter step dominating the cost of the full algorithm. The speed-up is achieved by designing an efficient algorithm for finding and implementing the isometry. The worst-case Toffoli cost of our isometry circuit, which may be viewed as a batched version of an approach by Malvetti et al., is essentially $2s$ for sufficiently large values of $n$, yielding roughly a $\log(s)/2$ improvement factor over the state-of-the-art. In numerical benchmarks on randomly chosen states, the cost is closer to $s$. With the improved isometry circuit, we examine the dense-state preparation step and present ways to optimize the joint cost of both steps, particularly in the case of target states with purely real coefficients, by outsourcing some sub-tasks from the dense-state preparation to the isometry.

Figures (11)

• Figure 1: Sparse state-preparation circuit. First, the coefficients of the sparse state $\ket{\Theta}$ are encoded into a dense state $\ket{\theta}$ within a subspace register; subsequently, this dense state is transformed into the target state $\ket{\Theta}$ via an isometry.
• Figure 2: (Left) Improvement factor of the Toffoli cost for implementing the isometry step in this work \ref{['eq:toffoli_cost']} over the method of Malvetti2021. For both approaches, we considered the worst-case cost. Since the upper bound \ref{['eq:toffoli_cost']} is quite loose when $s$ and $m$ are close, the improvement according to \ref{['eq:toffoli_cost']} reaches a maximum at a certain $n$ and then decreases, even though the actual improvement grows monotonically with $n$ toward an asymptote. At each $n$, we therefore take the maximum improvement factor from all $n' \leq n$ in order to avoid this misrepresentation. (Right) Number of Toffolis required for implementing the isometry step with our algorithm for random $s$-sparse states on $n$ qubits divided by $s$.
• Figure 3: Isometry circuit created by the algorithm in Malvetti2021, mapping $\ket{\Theta}$ to a $3$-qubit subspace. For each element outside the subspace, apply CX gates to obtain $\ket{k}^s\ket{e_j}^r$ for a $\ket{k}^s$ not yet present in the subspace and a $j\in \{0, \dots, 3\}$. Then, use a multi-controlled-X gate to transform $\ket{k}^s\ket{e_j}^r$ to $\ket{k}^s\ket{0}^r$. We index qubits from top to bottom and bitstrings from left to right.
• Figure 4: Our isometry circuit mapping $\ket{\Theta}$ to a $3$-qubit subspace. First, we create a batch $(\ket{0}^s\ket{e_0}^r, \dots, \ket{3}^s\ket{e_3}^r)$ using multi-controlled-CX gates and apply an unrestricted partial unary iteration PUI$_0^3$ with control interval $[\ket{0}^s, \ket{3}^s]$ to zero the qubits of the batch-states in the non-subspace register. Throughout the paper, we use rounded corners on boxes to emphasize that the qubits entering and exiting the box are not changed but merely serve as control qubits for the other parts of the operation. We repeat the procedure for the second batch $(\ket{4}^s\ket{e_0}^r, \dots, \ket{6}^s\ket{e_2}^r)$. The circuits for the PUIs are given in Figure \ref{['fig:unrestricted_pui']}. Moreover, the creation of the second batch within the dotted box is analyzed in detail in Figure \ref{['fig:batch']}.
• Figure 5: Creation of the second batch of the example in Figure \ref{['fig:isometry']} (dotted box). The first state is already in the correct form $\ket{4}^s\ket{e_0}^r$; for the second, we use a multi-target-CX gate (CMX) to bring it into batch form. Hereby, the upper indices denote target qubits, while the lower indices denote the control qubits. The last state requires a Toffoli gate controlled on the third qubit, where the purple states differ, and on the first subspace qubit, where they coincide. Subsequently, the last state is transformed so that the states constitute a full batch. The non-subspace register of the batch elements is then set to zero via an unrestricted partial unary iteration.

Theorems & Definitions (2)

• Lemma
• proof