A Grouped Sorting Queue Supporting Dynamic Updates for Timer Management in High-Speed Network Interface Cards

TL;DR

The paper addresses the need for high-precision, scalable, and dynamically updatable hardware timer management in NICs for SDN, RDMA, and TOE by introducing two key concepts: an update operation and a group sorting mechanism within a hardware priority queue. The authors implement a hybrid architecture combining a 1D systolic array and shift registers to realize a 4K-depth, 16-bit timer queue, achieving up to $>500$ MHz in a $28$ nm process (175 Mpps, 12 ns precision) and over $300$ MHz on FPGA (116 Mpps). The update operation enables dynamic priority changes through propagation of basic enqueue and remove actions, while group sorting handles overflow by partitioning the queue into two groups separated by a boundary $P_l$ (set as $P_l = 2^{W_r-1}$) to preserve correct dequeue timing after wraparound. The results show substantial reductions in LUTs and FFs compared to baselines like AnTiQ and demonstrate the approach’s applicability to flow-table timeout management and other dynamic timer-heavy NIC tasks, potentially informing hardware schedulers and anti-starvation mechanisms.

Abstract

With the hardware offloading of network functions, network interface cards (NICs) undertake massive stateful, high-precision, and high-throughput tasks, where timers serve as a critical enabling component. However, existing timer management schemes suffer from heavy software load, low precision, lack of hardware update support, and overflow. This paper proposes two novel operations for priority queues--update and group sorting--to enable hardware timer management. To the best of our knowledge, this work presents the first hardware priority queue to support an update operation through the composition and propagation of basic operations to modify the priorities of elements within the queue. The group sorting mechanism ensures correct timing behavior post-overflow by establishing a group boundary priority to alter the sorting process and element insertion positions. Implemented with a hybrid architecture of a one-dimension (1D) systolic array and shift registers, our design is validated through packet-level simulations for flow table timeout management. Results demonstrate that a 4K-depth, 16-bit timer queue achieves over 500 MHz (175 Mpps, 12 ns precision) in a 28nm process and over 300 MHz (116 Mpps) on an FPGA. Critically, it reduces LUTs and FFs usage by 31% and 25%, respectively, compared to existing designs.

Figures (10)

• Figure 1: Decomposition of basic operations
• Figure 2: Insertion Position by Group Sorting Rule
• Figure 3: Hybrid Architecture
• Figure 4: Systolic Unit
• Figure 5: Timing Graph of Propagating Operations