Probabilistic Computers for MIMO Detection: From Sparsification to 2D Parallel Tempering

TL;DR

This work tackles the scalability bottleneck of dense p-bit probabilistic computers by introducing graph sparsification with auxiliary copy variables, enabling fully on-chip parallel tempering for dense problems like MIMO detection. The authors demonstrate 1,920 p-bits on a single FPGA across 15 replicas to solve a 64×64 MIMO instance and project ASIC performance in 7 nm showing ~89 MHz operation at ~185 mW. They further address sensitivity to the copy-strength constraint with Two-Dimensional Parallel Tempering (2D-PT), which exchanges replicas along both temperature and constraint dimensions, delivering up to ~500× faster convergence and, in 128×128 MIMO, zero BER at high SNR where 1D-PT fails. Collectively, the results establish a scalable, tuning-free framework for dense combinatorial optimization on-chip, with implications for high-throughput wireless systems and long-term dense optimization architectures.

Abstract

Probabilistic computers built from p-bits offer a promising path for combinatorial optimization, but the dense connectivity required by real-world problems scales poorly in hardware. Here, we address this through graph sparsification with auxiliary copy variables and demonstrate a fully on-chip parallel tempering solver on an FPGA. Targeting MIMO detection, a dense, NP-hard problem central to wireless communications, we fit 15 temperature replicas of a 128-node sparsified system (1,920 p-bits) entirely on-chip and achieve bit error rates significantly below conventional linear detectors. We report complete end-to-end solution times of 4.7 ms per instance, with all loading, sampling, readout, and verification overheads included. ASIC projections in 7 nm technology indicate about 90 MHz operation with less than 200 mW power dissipation, suggesting that massive parallelism across multiple chips could approach the throughput demands of next-generation wireless systems. However, sparsification introduces sensitivity to the copy-constraint strength. Employing Two-Dimensional Parallel Tempering (2D-PT), which exchanges replicas across both temperature and constraint dimensions, we demonstrate over 10X faster convergence without manual parameter tuning. These results establish an on-chip p-bit architecture and a scalable algorithmic framework for dense combinatorial optimization.

Figures (6)

• Figure 1: (a) Multiple-input multiple-output (MIMO) detection: transmitted symbols pass through a noisy fading channel and must be recovered at the receiver. (b) The maximum-likelihood detection cost maps to an Ising Hamiltonian with all-to-all connectivity (left). Sparsification introduces auxiliary copy nodes connected by ferromagnetic couplings of strength $P$ (right). (c) On-chip parallel tempering with 15 temperature replicas instantiated entirely on an FPGA. Replicas exchange states along the inverse temperature ($\beta$) axis while $P$ remains fixed. (d) Two-Dimensional Parallel Tempering (2D-PT) arranges replicas on a grid, enabling exchanges along both $\beta$ and $P$ axes. This eliminates the need for manual $P$-tuning while improving mixing across energy barriers.
• Figure 2: (a) Preprocessing: a 64-node all-to-all MIMO problem is sparsified to 128 p-bits (two copies per node) and replicated across 15 inverse temperatures ($\beta$ values). All replicas are loaded onto the FPGA in $t_{\mathrm{load}} = 160$ ns. (b) On-chip parallel tempering: each step performs Monte Carlo sweeps, energy evaluation, and replica swaps, with total step time $t_{\mathrm{step}}$. (c) Verification: the best sparse configuration is projected to the original all-to-all graph via majority voting, and the energy is verified against the dense weight matrix in $t_{\mathrm{verify}} = 40$ ns. The complete solution time is $t_{\mathrm{instance}} = t_{\mathrm{load}} + N_{\mathrm{steps}} \times t_{\mathrm{step}} + t_{\mathrm{read}} + t_{\mathrm{verify}}$; all timing values are averaged over 13,000 instances. (d) Bit error rate versus SNR for $64 \times 64$ BPSK MIMO detection. On-chip parallel tempering significantly outperforms MMSE, achieving complete solution times of 4.7 ms ($N_{\mathrm{steps}}=1000$) and 47 ms ($N_{\mathrm{steps}}=10000$). (e) Residual energy $\rho^{f}_E = (E_{\mathrm{meas}} - E_{\mathrm{ground}})/N$ versus $N_{\mathrm{steps}}$ for several SNR values; upper axis shows corresponding wall-clock time. Error bars denote 95% bootstrap confidence intervals.
• Figure 3: Graphic Database System II (GDSII) layout for a $64 \times 64$ MIMO problem, mapped to a 64-node all-to-all graph and sparsified with two copies per node ($N=128$ physical p-bits). The design was generated using the ASAP7 predictive 7 nm Process Design Kit (PDK) via the mflowgen toolchain and follows a three-level hierarchy: (a) Top-level floorplan integrating 15 parallel replicas for 1D-PT, occupying a total integrated chip area of $10.6 \times 10.6$ mm$^2$ (including power, pins, and other overhead), with logic area occupying 55.9mm$^2$. (b) Layout of a single replica macro ($1.9 \times 1.9$ mm$^2$). (c) Detailed layout of an individual p-bit macro ($0.12 \times 0.12$ mm$^2$).
• Figure 4: (a) Residual energy per spin $\rho_E^{f}$ for the Sherrington--Kirkpatrick (SK) spin glass ($N=64$, two-copy sparsification) under 1D parallel tempering as a function of copy strength $P$. For smaller swap budgets, $\rho_E^{f}$ decreases with increasing $P$, reaches a minimum near $P \approx 1.5$, then increases as excessive copy strength traps the system in local minima. For larger swap budgets, the algorithm escapes these traps, yielding lower residual energies even at large $P$. (b) Copy-agreement percentage across the 2D replica grid ($\beta$ rows, $P$ columns) with $P \in [0.5, 2]$ reported in Table \ref{['tab:betaP_schedule']}. The multi-column $P$ ladder enforces near-perfect agreement ($>$ 99%) in the rightmost (high-$P$) column while allowing state exploration in low-$P$ columns. (c) Residual energy versus number of swaps. 2D-PT reaches the ground state for all instances in ${\approx}10^3$ swaps, whereas 1D-PT (using optimized $P$ at each budget) requires ${>}10^5$ swaps to reach a residual energy of $10^{-5}$. All data averaged over 100 instances $\times$ 100 trials, error bars denote 95% bootstrap confidence intervals.
• Figure 5: (a) Bit error rate (BER) versus signal-to-noise ratio (SNR) for $128\times128$ BPSK MIMO detection, averaged over 200 channels and 10 transmitted symbols per channel. All instances are sparsified with two copies per node (256 p-bits per replica). 1D-PT results are shown for two swap budgets ($N_{\mathrm{swaps}}=2,000$ and $20{,}000$) using a 16-replica $\beta$ ladder; increasing the budget by $10\times$ improves performance but 1D-PT still exhibits an error floor at high SNR. 2D-PT uses a $16\times13$ replica array with the same $\beta$ values and a distinct $P$ per column (values in Table \ref{['tab:betaP_schedule']}), achieving substantially lower BER and reaching zero errors at high SNR. For both methods, the final solution is selected as the minimum-energy state after mapping back to the all-to-all problem; for 2D-PT, this selection is restricted to the coldest replicas (last row). (b,c) Mean swap probabilities along the $P$-axis and $\beta$-axis, respectively, averaged over all rows and columns.