Plutarch: Toward Scalable Operational Parallelism on Racetrack-Shaped Trapped-Ion Processors

TL;DR

Plutarch tackles the challenge of achieving scalable parallelism on racetrack-shaped trapped-ion processors by combining unitary decomposition, locality-aware in-place scheduling, and hardware-aware shortcuts. The framework demonstrates that naive zone expansion can hurt performance due to ion-circulation overhead, and shows substantial runtime and fidelity gains across near-term and fault-tolerant benchmarks. Key contributions include an efficient 2Q gate placement strategy, a linear-time phase gadget generator, and a block-aware scheduling paradigm that reduces circulation while preserving parallelism. Hardware modifications, such as shortcuts and nonuniform layouts, further enhance scalability, reducing shuttling costs and enabling more efficient large-scale ECC encoding. Collectively, Plutarch offers a practical pathway toward scalable racetrack quantum computing with tangible reductions in end-to-end runtime and improved resilience to decoherence and transport errors.

Abstract

A recent advancement in quantum computing shows a quantum advantage of certified randomness on the racetrack processor. This work investigates the execution efficiency of this architecture for general-purpose programs. We first explore the impact of increasing zones on runtime efficiency. Counterintuitively, our evaluations using variational programs reveal that expanding zones may degrade runtime performance under the existing scheduling policy. This degradation may be attributed to the increase in track length, which increases ion circulation overhead, offsetting the benefits of enhanced parallelism. To mitigate this, the proposed \textit{Plutarch} exploits 3 strategies: (i) unitary decomposition and translation to maximize zone utilization, (ii) prioritizing the execution of nearby gates over ion circulation, and (iii) implementing shortcuts to provide the alternative path.

Figures (14)

• Figure 1: A racetrack architecture decross2024computational. (a) Top zones (purple), which perform ion reordering operations but do not execute gate operations, and bottom zones (blue), capable of both gate operations and ion reordering. Each of the top and bottom regions consists of 4 gate zones. (b) Ion reordering operations (Swap, Shift, Split, and Combine). (c) 2-qubit gate operation, which is possible only when ions are arranged in a combined structure of Yb-Ba-Ba-Yb. (d) Single-qubit gate operation to the left-side qubits of each pair after splitting the ions' crystal structures. (e) Single-qubit gate operation to the right-side qubits of each pair after splitting the ions' crystal structures.
• Figure 2: Program runtime analysis by the rolodex scheduling decross2024computational according to the number of gate operation zones in the racetrack architecture using 32-qubit QAOA (with target graphs of path-shaped tannu2019ensemble, 2-regular marwaha2021local, and Sherrington-Kirkpatrick model farhi2022quantum) and VQE (phase gadget Cowtan_2020, 2-local HWEA li2024case, and circular-shaped efficient SU2 wang2023prepare) programs. The current H2 processor QuantinuumH2Datasheetmoses2023race utilizes 4 operation zones.
• Figure 3: An example of the efficient gate decomposition and translation for an 8-qubit Z-phase gadget. As shown in the left half of the picture, a CX chain structure whose circuit depth expands logarithmically cruz2019efficientjang2025qubit according to the number of qubits is adopted to maximize the utilization of zones. In order to minimize the ion reordering overhead, the inner chain is gradually formed at the center of the chain. In the right half of the picture, most CX gates are translated to the ion's native gates. The innermost chain of two CXs and one RZ can be directly implemented as a single native ZZ-interaction operation. Although the translated representation omits the right-half operations, they can be executed by applying the gates in the reverse order, analogous to the left-half gate chain.
• Figure 4: Comparison of runtime and zone utilization for various Z-phase gadgets (Ladder, Fountain, Parallel, and Parallel+RZZ) according to different qubits. Lower runtime and higher zone utilization mean better performance, respectively.
• Figure 5: Detailed execution scheduling comparison of 4-qubit single-layer QAOA circuits for the 4-node 2-regular target graph. (a) shows the execution of the existing rolodex scheduling decross2024computational, and (b) shows the execution of the proposed scheduling. For ease of understanding, it is considered for the racetrack electrode with two bottom gate zones and top reordering zones, respectively. For (a), the top zones of the racetrack electrode are utilized for ion rearrangement (it can be confirmed from the flipped numbering of ions), but for (b), both ion rearrangement and gate operations are processed using only the bottom zones. (c) shows a detailed ion rearrangement process on the top zones for two-qubit operations.