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Bio-RV: Low-Power Resource-Efficient RISC-V Processor for Biomedical Applications

Vijay Pratap Sharma, Annu Kumar, Mohd Faisal Khan, Mukul Lokhande, Santosh Kumar Vishvakarma

TL;DR

Bio-RV addresses the need for a deterministic, low-power RISC-V controller suitable for safety-critical biomedical devices. It introduces a non-pipelined, multi-cycle RV32I architecture with explicit execution control and external instruction loading, enabling controlled firmware deployment and post-silicon validation. The design emphasizes minimal hardware complexity and easy FPGA-ASIC portability, validated by 180 nm post-layout results showing a small footprint and low energy per cycle. This work demonstrates a practical, flexible host-controller core for biomedical SoCs that manage accelerators and sensor subsystems in implantable devices, prioritizing reliability and integration over peak performance.

Abstract

This work presents Bio-RV, a compact and resource-efficient RISC-V processor intended for biomedical control applications, such as accelerator-based biomedical SoCs and implantable pacemaker systems. The proposed Bio-RV is a multi-cycle RV32I core that provides explicit execution control and external instruction loading with capabilities that enable controlled firmware deployment, ASIC bring-up, and post-silicon testing. In addition to coordinating accelerator configuration and data transmission in heterogeneous systems, Bio-RV is designed to function as a lightweight host controller, handling interfaces with pacing, sensing, electrogram (EGM), telemetry, and battery management modules. With 708 LUTs and 235 flip-flops on FPGA prototypes, Bio-RV, implemented in a 180 nm CMOS technology, operate at 50 MHz and feature a compact hardware footprint. According to post-layout results, the proposed architectural decisions align with minimal energy use. Ultimately, Bio-RV prioritises deterministic execution, minimal hardware complexity, and integration flexibility over peak computing speed to meet the demands of ultra-low-power, safety-critical biomedical systems.

Bio-RV: Low-Power Resource-Efficient RISC-V Processor for Biomedical Applications

TL;DR

Bio-RV addresses the need for a deterministic, low-power RISC-V controller suitable for safety-critical biomedical devices. It introduces a non-pipelined, multi-cycle RV32I architecture with explicit execution control and external instruction loading, enabling controlled firmware deployment and post-silicon validation. The design emphasizes minimal hardware complexity and easy FPGA-ASIC portability, validated by 180 nm post-layout results showing a small footprint and low energy per cycle. This work demonstrates a practical, flexible host-controller core for biomedical SoCs that manage accelerators and sensor subsystems in implantable devices, prioritizing reliability and integration over peak performance.

Abstract

This work presents Bio-RV, a compact and resource-efficient RISC-V processor intended for biomedical control applications, such as accelerator-based biomedical SoCs and implantable pacemaker systems. The proposed Bio-RV is a multi-cycle RV32I core that provides explicit execution control and external instruction loading with capabilities that enable controlled firmware deployment, ASIC bring-up, and post-silicon testing. In addition to coordinating accelerator configuration and data transmission in heterogeneous systems, Bio-RV is designed to function as a lightweight host controller, handling interfaces with pacing, sensing, electrogram (EGM), telemetry, and battery management modules. With 708 LUTs and 235 flip-flops on FPGA prototypes, Bio-RV, implemented in a 180 nm CMOS technology, operate at 50 MHz and feature a compact hardware footprint. According to post-layout results, the proposed architectural decisions align with minimal energy use. Ultimately, Bio-RV prioritises deterministic execution, minimal hardware complexity, and integration flexibility over peak computing speed to meet the demands of ultra-low-power, safety-critical biomedical systems.
Paper Structure (7 sections, 3 figures, 3 tables)

This paper contains 7 sections, 3 figures, 3 tables.

Table of Contents

  1. Introduction
  2. BIO-RV architecture
  3. Micro-architectural Overview
  4. External Instruction Loading and Explicit Execution Control
  5. FPGA–ASIC Friendly Implementation
  6. Performance Evaluation
  7. Conclusion

Figures (3)

  • Figure 1: Typical TinyML SoC architecture for biomedical iPacE-CHIP applications, highlighting the Bio-RV host processor and interfaced accelerator architecture and pacing, sensing, electrogram (EGM), telemetry, and battery management blocks.
  • Figure 2: Detailed Data-path for the proposed Bio-RV processor
  • Figure 3: Final GDS-II layout of the Bio-RV implemented in 180 nm CMOS technology, including I/O pad directions.