Matrix-PIC: Harnessing Matrix Outer-product for High-Performance Particle-in-Cell Simulations

TL;DR

MatrixPIC tackles the deposition bottleneck in PIC simulations by reimagining current deposition as dense matrix outer-product operations on Matrix Processing Units (MPUs) within a hybrid VPU-MPU framework. It introduces a rhocell data layout to prevent atomic conflicts, a GPMA-based incremental sorting strategy to sustain data locality, and a global resort policy to balance long-term performance. The approach delivers substantial end-to-end speedups, notably up to 2.63 times in LWFA workloads and 8.7 times in third-order QSP deposition, while achieving high hardware utilization (around 83 percent of theoretical CPU peak). This work demonstrates that architecture-aware co-design for high-density matrix accelerators can outperform optimized GPU implementations in particle-based simulations and motivates broader adoption on MPU-enabled CPUs.

Abstract

Particle-in-Cell (PIC) simulations spend most of their execution time on particle--grid interactions, where fine-grained atomic updates become a major bottleneck on traditional many-core CPUs. Recent CPU architectures integrate specialized Matrix Processing Units (MPUs) that efficiently support matrix outer-product operations, offering new opportunities to overcome this limitation. Leveraging this architectural shift, this work focuses on redesigning the current deposition step of PIC simulations under a matrix-centric execution model. We present MatrixPIC, the first holistic co-design of the deposition kernel, data layout, and incremental particle sorting tailored to the hybrid MPU--VPU SIMD model on modern CPUs. MatrixPIC introduces: (i)~a block-matrix formulation of the current deposition algorithm that maps naturally to MPU outer-product primitives; (ii)~a hybrid execution pipeline that combines MPU-based high-density accumulation with VPU-based data preparation and control flow; and (iii)~an $O(1)$-amortized incremental sorter based on a gapped packed-memory array to preserve data locality for efficient MPU execution. Evaluated on a next-generation HPC platform, MatrixPIC achieves significant performance gains. In Laser-Wakefield Acceleration (LWFA) simulations, it delivers up to $2.63\times$ speedup in total runtime. For third-order deposition, the core kernel is accelerated by $8.7\times$ over the baseline and $2.0\times$ over the best hand-optimized VPU implementation. Moreover, MatrixPIC reaches $83.08\%$ of theoretical CPU peak performance, nearly $2.8\times$ higher than a highly optimized CUDA kernel on a data center GPU. These results demonstrate the effectiveness of matrix-oriented co-design for accelerating PIC simulations on emerging CPU architectures.

Figures (10)

• Figure 1: Runtime breakdown of uniform plasma PIC simulation on the Tianhe Xingyi HPC platform. (We utilize WarpX v24.07WarpX2022 with a 30-million cells and 4.3 billion particles)
• Figure 2: Illustration of SIMD current deposition leading to potential write conflicts on a grid node.
• Figure 3: Conceptual illustration of the rhocell data layout for different interpolation schemes Vincenti2017SIMD. (a) The first-order CIC scheme. (b) The third-order QSP scheme.
• Figure 4: GPMA: gaps between blocks enable efficient local index updates.
• Figure 5: MPU outer product for current deposition. Left: In CIC schema, 2 particle ($p_1, p_2$) contributions (16 values total) computed within logical $4 \times 8$ outer product operation. Right: In QSP schema, 2 particle ($p_1, p_2$) contributions (32 values total) computed within logical $8 \times 8$ outer product operation.