Quantum State Discrimination Enhanced by FPGA-Based AI Engine Technology

TL;DR

The paper tackles the latency and resource challenges of quantum state discrimination for superconducting qubits by moving the discrimination task to an AMD Versal AI Engine on a Xilinx VCK190 board. It presents a multi-layer neural-network discriminator mapped to the AI Engine, with a streaming PL pipeline ensuring real-time inference. Key results show a kernel latency of $81.6$ ns at $1250$ MHz and a very small resource footprint ($0.25\%$ kernel tiles), with power around $0.593$ W, demonstrating feasibility for real-time mid-circuit measurement and scalability to larger quantum systems including $qutrits$ and $qudits$. The work lays groundwork for scalable, real-time quantum control using heterogeneous architectures and signals a path toward multi-kernel parallelism and closed-loop feedback on Versal-based systems.

Abstract

Identifying the state of a quantum bit (qubit), known as quantum state discrimination, is a crucial operation in quantum computing. However, it has been the most error-prone and time-consuming operation on superconducting quantum processors. Due to stringent timing constraints and algorithmic complexity, most qubit state discrimination methods are executed offline. In this work, we present an enhanced real-time quantum state discrimination system leveraging FPGA-based AI Engine technology. A multi-layer neural network has been developed and implemented on the AMD Xilinx VCK190 FPGA platform, enabling accurate in-situ state discrimination and supporting mid-circuit measurement experiments for multiple qubits. Our approach leverages recent advancements in architecture research and design, utilizing specialized AI/ML accelerators to optimize quantum experiments and reduce the use of FPGA resources.

Figures (6)

• Figure 1: Architecture of the Classical Control System: On the left, the User Host PC depicts the software-level interactions, starting from the high-level algorithm through to circuit representation and Quantum Assembly Language (QASM). The central section shows the architecture of the classical control system, comprising a Control Core and functional units (FUs), Quantum State Discriminator (QSD), filtering, and error decoding. Interfaces facilitate communication with various components. On the right, the diagram highlights the downstream components such as Arbitrary Waveform Generators (AWGs), memory modules (MEM), Digital-to-Analog Converters (DACs), and Analog-to-Digital Converters (ADCs) which interact with the Filters & Amplifiers before connecting to the quantum chip.
• Figure 2: Visualization of Qubit State Readout in the IQ Plane. The figure displays clusters of data points representing the In-phase (I) and Quadrature (Q) components of the readout signal during the measurement of a qubit's state. The blue points correspond to the 0-State, while the red points correspond to the 1-State. Each cluster is centered around a mean value, indicated by the black dots, illustrating the distinct distributions of measurement outcomes for the two quantum states.
• Figure 3: Overview of the AI Engine Architecture: (a) AI Engine Interfaces illustrating connections between the Processing System (PS), Programmable Logic (PL), and Input/Output (I/O); (b) Configuration of AI Engine Tiles featuring interconnected AI cores and memory resources; (c) Detailed structure of the AI Engine Core, showing the local memory, ISA-based vector processor, and interconnects for data movement and vector processing capabilities xilinx2023versal.
• Figure 4: Architecture of a Multi-Layer Neural Network. In Layer 1, the input data is represented as a combination of In-phase (I) and Quadrature (Q) components. The data is processed through weighted connections and biases, resulting in the Layer 1 output after applying the ReLU activation function. Layer 2 takes the output from Layer 1 and again processes it using its own set of weights and biases, culminating in the Layer 2 output. Finally, Layer 3 further processes this output to yield the final output $L_3$, incorporating its own weights and biases. Each layer demonstrates how neural networks compute outputs through weighted summations and activation functions, illustrating the fundamental principles of neural network architecture.
• Figure 5: Execution timeline of functions on the AI Engine. The initialization phase is followed by two iterations of the main program, each invoking the neural network kernel. Measured execution times for initialization, main execution, and NN run are shown.