TranSC: Hardware-Aware Design of Transcendental Functions Using Stochastic Logic

TL;DR

TranSC introduces a hardware-efficient stochastic-computing framework for transcendental functions by replacing conventional RNGs with Van der Corput low-discrepancy sequences in a single, unified BSG. This eliminates mid-stage decorrelators, significantly reducing area, power, and energy while achieving higher accuracy across trig, exponential, and activation functions. The paper demonstrates strong decorrelation (low SCC, near-zero ZCE) and verifies practical gains in use cases like 2D image transformation and robotic arm positioning, with a FoM that combines accuracy and hardware costs. Compared to CORDIC and PPI, TranSC offers a favorable trade-off for resource-constrained systems, paving the way for end-to-end SC architectures in low-power AI and robotics. The work also highlights the hardware efficiency of the VDC-$2^n$ BSG and its ability to generate multiple independent streams from a single counter.

Abstract

The hardware-friendly implementation of transcendental functions remains a longstanding challenge in design automation. These functions, which cannot be expressed as finite combinations of algebraic operations, pose significant complexity in digital circuit design. This study introduces a novel approach, TranSC, that utilizes stochastic computing (SC) for lightweight yet accurate implementation of transcendental functions. Building on established SC techniques, our method explores alternative random sources-specifically, quasi-random Van der Corput low-discrepancy (LD) sequences-instead of conventional pseudo-randomness. This shift enhances both the accuracy and efficiency of SC-based computations. We validate our approach through extensive experiments on various function types, including trigonometric, hyperbolic, and activation functions. The proposed design approach significantly reduces MSE by up to 98% compared to the state-of-the-art solutions while reducing hardware area, power consumption, and energy usage by 33%, 72%, and 64%, respectively.

Figures (10)

• Figure 1: A general SC system architecture with BSG, CLB, and output decoder that converts the output bit-stream to standard radix representation.
• Figure 2: Bit-stream generation using RNG and comparator (a) Shared RNG for correlated bit-streams. (b) Independent RNGs for uncorrelated bit-streams.
• Figure 3: Conventional designs of simple polynomial functions in SC, (a) Quadratic function ($x^2$), (b) Cubic function ($x^3$), (c) Quartic function ($x^4$), and (d) Quintic function ($x^5$).
• Figure 4: The overall design of the state-of-the-art RNGs (a) LFSR design (8-bit); maximal length LFSR with polynomial $x^8+x^7+x^6+1$ is demonstrated as an example, and (b) Sobol design.
• Figure 5: The overall designs of VDC-$2^n$ RNGs using binary up counter (a) VDC-$2$; reversing every single bit of the counter output, (b) VDC-$4$; reversing every 2-bit subgroup of counter outputs, (c) VDC-$8$; reversing every 3-bit subgroup of counter outputs, and (d) VDC-$16$; reversing every 4-bit subgroup of counter outputs. All designs are considered as $n$-bit precision - the same circuit is used with different hardwiring.