Neuromorphic FPGA Design for Digital Signal Processing
Justin London
TL;DR
Neuromorphic FPGA design for DSP addresses implementing FIR and IIR filters on FPGAs using memristor-based spiking neural networks, enabling in-memory computation and on-chip learning with $y(n)=\sum_{k=0}^{M-1} b_k x(n-k)$ for FIR and $y[n]=\sum_{k=0}^{M} b_k x[n-k] - \sum_{k=1}^{N} a_k y[n-k]$ for IIR. It leverages event-driven processing via Leaky Integrate-and-Fire neurons and time-domain modules (including $z^{-1}$ multipliers) to map DSP operations to spiking hardware, validated by Verilog/Vivado designs and LTSpice memristor models. The study compares neuromorphic designs against conventional von Neumann DSP, highlighting potential reductions in latency and power while allowing on-chip learning through spike-timing-dependent plasticity, albeit at a cost to numerical precision. Results show that the neuromorphic IIR can closely approximate classical IIR, while the neuromorphic FIR exhibits greater variability and higher MSE, illustrating energy-precision trade-offs and motivating further precision improvements and real-FPGA implementations.
Abstract
In this paper, the foundations of neuromorphic computing, spiking neural networks (SNNs) and memristors, are analyzed and discussed. Neuromorphic computing is then applied to FPGA design for digital signal processing (DSP). Finite impulse response (FIR) and infinite impulse response (IIR) filters are implemented with and without neuromorphic computing in Vivado using Verilog HDL. The results suggest that neuromorphic computing can provide low-latency and synaptic plasticity thereby enabling continuous on-chip learning. Due to their parallel and event-driven nature, neuromorphic computing can reduce power consumption by eliminating von Neumann bottlenecks and improve efficiency, but at the cost of reduced numeric precision.