DS-CIM: Digital Stochastic Computing-In-Memory Featuring Accurate OR-Accumulation via Sample Region Remapping for Edge AI Models

TL;DR

DS-CIM tackles the trade-off between stochastic computing accuracy and digital CIM throughput by introducing a unipolar OR-MAC design with 64× replication and a shared PRNG-based 2D sampling remapping to eliminate 1s saturation. The approach preserves accuracy while delivering high energy efficiency (TOPS/W) and area efficiency, enabling edge-scale MVM for CNNs and transformers. Key contributions include a pair of DS-CIM variants (DS-CIM1 for accuracy and DS-CIM2 for efficiency), a data-remapping strategy to remove saturation errors, and validated results on ResNet18/50 and LLaMA-7B. The work demonstrates that stochastic CIM can achieve competitive accuracy with substantial hardware efficiency, making it practical for large models on edge devices.

Abstract

Stochastic computing (SC) offers hardware simplicity but suffers from low throughput, while high-throughput Digital Computing-in-Memory (DCIM) is bottlenecked by costly adder logic for matrix-vector multiplication (MVM). To address this trade-off, this paper introduces a digital stochastic CIM (DS-CIM) architecture that achieves both high accuracy and efficiency. We implement signed multiply-accumulation (MAC) in a compact, unsigned OR-based circuit by modifying the data representation. Throughput is enhanced by replicating this low-cost circuit 64 times with only a 1x area increase. Our core strategy, a shared Pseudo Random Number Generator (PRNG) with 2D partitioning, enables single-cycle mutually exclusive activation to eliminate OR-gate collisions. We also resolve the 1s saturation issue via stochastic process analysis and data remapping, significantly improving accuracy and resilience to input sparsity. Our high-accuracy DS-CIM1 variant achieves 94.45% accuracy for INT8 ResNet18 on CIFAR-10 with a root-mean-squared error (RMSE) of just 0.74%. Meanwhile, our high-efficiency DS-CIM2 variant attains an energy efficiency of 3566.1 TOPS/W and an area efficiency of 363.7 TOPS/mm^2, while maintaining a low RMSE of 3.81%. The DS-CIM capability with larger models is further demonstrated through experiments with INT8 ResNet50 on ImageNet and the FP8 LLaMA-7B model.

Figures (7)

• Figure 1: Principles of Stochastic Computing and Digital CIM.
• Figure 2: (a) Overall architecture of proposed DS-CIM. (b) Demonstration of the proposed unipolar OR-MAC configurations with the accuracy-oriented OR-MAC16 configuration for DS-CIM1 and the efficiency-oriented OR-MAC64 configuration for DS-CIM2. (c) Effcient latch-cached accumulator for reducing the high energy consumption of the conventional accumulators.
• Figure 3: (a) Bipolar OR-MAC81 for event camera in yang2024278. (b) Proposed unipolar OR-MAC64 circuit with only 0.4ns latency in 40nm process.
• Figure 4: An illustration of achieving 32x latency reduction and 32x compute density increment by increasing CMR from 1 to 64.
• Figure 5: Memory-friendly pipelined layer channel input timing diagram of the DS-CIM macro with CMR=64 and bitstream length=256.