Magnetic exchange coupled nonreciprocal devices for cryogenic memory

TL;DR

The paper addresses the need for dense, low-power cryogenic memory compatible with SFQ logic, proposing an exchange-coupled EuS/V/EuS trilayer platform for nonvolatile superconducting memory. Superconductivity is controlled by FI magnetization alignment through exchange coupling $\Delta_{ex}$ relative to the superconducting gap $\Delta_{sc}$, enabling switching from superconducting to resistive states; HAMR heats the FI to toggle between AP and P configurations. Key results include infinite magnetoresistance with $T_c^{\mathrm{P}} \approx 3.11$ K and $T_c^{\mathrm{AP}} \approx 3.51$ K, and selective single-cell switching by current pulses (e.g., 8 mA, 1 s) facilitating nonvolatile memory operation; below $T_c$, devices exhibit strong nonreciprocity as superconducting diodes with zero-field efficiencies up to $\eta \approx \pm 60\%$ (and up to $\approx \pm 80\%$ in some devices), enabling programmable pulse routing. The approach offers scalable, energy-efficient cryogenic memory and logic, with potential integration into SFQ circuits alongside Josephson junctions and possible synergy with Majorana-based qubits for quantum computing.

Abstract

As computing power demands continue to grow, superconducting electronics present an opportunity to reduce power consumption by increasing the energy efficiency of digital logic and memory. A key milestone for scaling this technology is the development of efficient superconducting memories. Such devices should be nonvolatile, scalable to high integration density and memory capacity, enable fast and low-power reading and writing operations, and be compatible with the digital logic. We present a versatile device platform to develop such nonvolatile memory devices consisting of an exchange-coupled ultra-thin superconductor encapsulated between two ferromagnetic insulators (FIs). The superconducting exchange coupling, which is tuneable by the relative alignment between the FI magnetizations, enables the switching of superconductivity on and off. We exploit this mechanism to create a superconducting nonvolatile memory where single-cell writing is realized using heat-assisted magnetic recording, and explain how it can become a contender for state-of-the-art superconducting memories. Furthermore, below their critical temperatures, the memory elements show a marked nonreciprocity, with zero magnetic field superconducting diode efficiencies exceeding $\pm$60%, showing the versatility of the proposed devices for superconducting computing.

Figures (4)

• Figure 1: Proposed superconducting memory functionality and superconducting exchange coupling in an EuS/V/EuS-based thin film multilayer. (a) Illustration of trilayer operation. When the magnetizations are parallel (P), the exchange coupling ($\Delta_\mathrm{ex}$) —which exceeds the superconducting gap ($\Delta_\mathrm{sc}$)— disrupts the Cooper pairs in the V layer, leading to a reduction in the critical temperature ($T_c$). When the EuS magnetizations (red arrows) are anti-parallel (AP), the total $\Delta_\mathrm{ex}$ is reduced and the superconductivity in V is preserved. (b) Spin-resolved density of states in V for P magnetization alignment. (c) Experimental temperature ($T$) dependence of the resistance of a 6 nm V film in the P and AP alignment configurations illustrated by the insets. $R_\mathrm{n}$ is the normal state resistance. (d) Experimental infinite magnetoresistance where the superconductivity is switched on and off by controlling the magnetization alignment using an in-plane magnetic field ($\mu_0 H_\parallel$), establishing the foundation of the proposed nonvolatile memory. The arrows indicate the $\mu_0 H_\parallel$ sweep directions and the insets show the magnetization alignments. (e) and (f) Proposed switching mechanism. (e) A tiny magnetic field is not sufficient to switch the magnetization configuration but, when local heating increases the device temperature (f), the magnetizations become P and superconductivity is switched off.
• Figure 2: Superconducting exchange coupling and infinite magnetoresistance in a patterned device. (a) Device geometry. The darker areas are etched, and the scale bar is 20 $\mu$m. The measurement circuit (black) and the magnetic field direction (red) are also shown. (b) $T$-dependence of the device resistance in the P and AP magnetic configurations, as indicated by the red arrows in the sketches, showing a critical temperature difference $\Delta T_c\approx0.4$ K. The V thickness $t_V$ is 7 nm. (c) Infinite magnetoresistance under a magnetic field applied along $y$ ($\mu_0H_\mathrm{y}$) at a temperature $T=3.3$ K. The horizontal arrows indicate the $\mu_0H_\mathrm{y}$ sweep directions, and the magnetization alignments are shown in Fig. \ref{['Figure1']}d.
• Figure 3: Resistive switches of an individual device using current pulses. (a) Upper panel, nonvolatile memory functioning showing that both superconducting and resistive states are stable at zero magnetic field. Lower panel, stepwise change of $\mu_0H_\mathrm{y}$ vs. time. (b) Measurement sequence: first, the magnetizations are set AP with an external magnet and a magnetic field $\mu_0H_\mathrm{y}{}\approx 0.3$ mT is applied. Next, an 8 mA current pulse is applied to switch the magnetization of the upper EuS layer, and make the 7-nm-thick V resistive. The process is repeated three times. (c) Sample geometry coloured as Fig. \ref{['Figure2']}a. Devices 1 and 2, separated by 100 $\mu$m, are marked by red rectangles. The current pulse is applied only to Device 1. (d) Resistance switches between superconducting and resistive states of Device 1 ($R_1$) normalized by its $R_\mathrm{n}$. (e) Device 2 resistance ($R_2$) normalized by its $R_\mathrm{n}$. (f) Current pulses ($I_1$, blue rectangles) and (g) magnetic field pulses (green rectangles) used to induce resistive switches to Device 1 without influencing Device 2. The measurements are performed at $T=3.3$ K.
• Figure 4: Three-state superconducting diode effect at 2.3 K. (a) Schematic illustrating the out-of-plane fringe magnetic fields ($B_z$) induced by the EuS layers in the anti-parallel alignment. The V thickness is 8 nm. (b) Measured current ($I$)-voltage ($V$) characteristics of SD1 at $\mu_0H_\mathrm{y}{}=2$ mT showing the forward ($I_\mathrm{c}^+$), reverse ($I_\mathrm{c}^-$), and retrapping ($I_\mathrm{r}$) currents. (c) and (d) $I_\mathrm{c}^+$ and $I_\mathrm{c}^-$ as a function of $\mu_0H_\mathrm{y}$ at 2.3 K. The black arrows indicate the sweep direction, and the magnetization alignments are schematically shown in the insets. (e) Three-state superconducting diode (SD) with forward, reversed, and resistive (low critical current) states allows for pulse propagation towards the right, left, or blocks propagation in either direction, respectively. (f) Programmable pulse propagation using the achieved SDs. Upper panel, a signal pulse injected through the upper arm can flow back into the lower arm when using a reversed diode to block incoming pulses, resulting in a pulse splitter. Lower panel, when using the resistive state of the proposed SDs to block pulses, propagation in the lower arm is prevented in both forward and reverse directions, enabling a pulse merger. Both schematics showcase the enhanced flexiblility of the proposed SDs for pulse guiding schemes. The pulses in (e) and (f) represent SFQ pulses.