Influence of Parallelism in Vector-Multiplication Units on Correlation Power Analysis

TL;DR

This work addresses the confidentiality risk of edge-deployed neural networks against power-based side-channel attacks by examining how parallelism in vector-multiplication accelerators affects correlation power analysis (CPA). It develops a theoretical model of power consumption for parallel neuron processing, derives an exponential decay form for the correct-weight correlation with increasing parallelism, and validates the predictions with FPGA-based experiments. The key finding is a practical security boundary: approximately 15 parallel operations in the same-input vector-multiplication unit render CPA using global power ineffective for weight extraction, with real hardware showing lower robustness (around 8 parallel) due to noise and non-ideal effects. These results inform accelerator design and countermeasure choices, suggesting masking or shuffling for small parallelisms and additional protections or local measurements for higher degrees of parallelism.

Abstract

The use of neural networks in edge devices is increasing, which introduces new security challenges related to the neural networks' confidentiality. As edge devices often offer physical access, attacks targeting the hardware, such as side-channel analysis, must be considered. To enhance the performance of neural network inference, hardware accelerators are commonly employed. This work investigates the influence of parallel processing within such accelerators on correlation-based side-channel attacks that exploit power consumption. The focus is on neurons that are part of the same fully-connected layer, which run parallel and simultaneously process the same input value. The theoretical impact of concurrent multiply-and-accumulate operations on overall power consumption is evaluated, as well as the success rate of correlation power analysis. Based on the observed behavior, equations are derived that describe how the correlation decreases with increasing levels of parallelism. The applicability of these equations is validated using a vector-multiplication unit implemented on an FPGA.

Figures (9)

• Figure 1: Hardware implementation of a vector-multiplication.
• Figure 2: Theoretical decrease of a single if other operate in parallel. The converges against zero when more than 16 operate in parallel. $10,000$ simulations are used for each number of to calculate the averaged .
• Figure 3: Maximum absolute correlation coefficients between $H_{\text{cw,}\tau}$ and the power consumed by another parallel operating for different points in time $\tau$. The results are generated by $10,000$ simulations for random weight and input values.
• Figure 4: Absolute correlation coefficient for all possible hypotheses and an increasing number of parallel operating . The results are averaged based on $10,000$ simulations. The first multiplication is targeted in (a). For (b) and (c), the switching to the fourth or eighth result is used. Interpolated functions that describe the decrease of the correlation coefficient for different $\tau$ are depicted in (d), where the results for the dashed lines are based on $10,000$ simulation runs.
• Figure 5: In (a), the correlation coefficient for $H_{cw}$ is shown as a function of the achieved . The results are averaged based on $10,000$ simulations. The confidence interval in (a) is calculated based on the targeted moments in time ranging from $\tau = 0$ to $\tau = 7$, while the solid red line indicates the mean value. The green points denote where the is high enough to conduct a successful . In (b), these points are also marked, indicating the based on the number of employed. These points correspond to the same number of as described in \ref{['sec:cpa_mul_array']}.