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LACIN: Linearly Arranged Complete Interconnection Networks

Ramón Beivide, Cristóbal Camarero, Carmen Martínez, Enrique Vallejo, Mateo Valero

TL;DR

LACIN introduces linearly arranged complete interconnection networks by enforcing identically indexed port connections (isoport) to link switches, thereby simplifying wiring and routing in CINs. The work characterizes port-pairing matrices, contrasts isoport (Circle and XOR) with anisoport (Swap), and presents minimal-routing schemes that avoid deadlock in the minimal-path regime. It then sections LACIN as a practical, linear CIN implementation, analyzes wiring length and crossing properties, and demonstrates applicability to large-scale topologies like HyperX and Dragonfly, including rack- and rack-to-rack deployments. The findings suggest substantial reductions in wiring complexity and improved deployability for both on-chip and large-scale interconnects, with trade-offs between simplicity (Circle) and implementation constraints (XOR).

Abstract

Several interconnection networks are based on the complete graph topology. Networks with a moderate size can be based on a single complete graph. However, large-scale networks such as Dragonfly and HyperX use, respectively, a hierarchical or a multi-dimensional composition of complete graphs. The number of links in these networks is huge and grows rapidly with their size. This paper introduces LACIN, a set of complete graph implementations that use identically indexed ports to link switches. This way of implementing the network reduces the complexity of its cabling and its routing. LACIN eases the deployment of networks for parallel computers of different scales, from VLSI systems to the largest supercomputers.

LACIN: Linearly Arranged Complete Interconnection Networks

TL;DR

LACIN introduces linearly arranged complete interconnection networks by enforcing identically indexed port connections (isoport) to link switches, thereby simplifying wiring and routing in CINs. The work characterizes port-pairing matrices, contrasts isoport (Circle and XOR) with anisoport (Swap), and presents minimal-routing schemes that avoid deadlock in the minimal-path regime. It then sections LACIN as a practical, linear CIN implementation, analyzes wiring length and crossing properties, and demonstrates applicability to large-scale topologies like HyperX and Dragonfly, including rack- and rack-to-rack deployments. The findings suggest substantial reductions in wiring complexity and improved deployability for both on-chip and large-scale interconnects, with trade-offs between simplicity (Circle) and implementation constraints (XOR).

Abstract

Several interconnection networks are based on the complete graph topology. Networks with a moderate size can be based on a single complete graph. However, large-scale networks such as Dragonfly and HyperX use, respectively, a hierarchical or a multi-dimensional composition of complete graphs. The number of links in these networks is huge and grows rapidly with their size. This paper introduces LACIN, a set of complete graph implementations that use identically indexed ports to link switches. This way of implementing the network reduces the complexity of its cabling and its routing. LACIN eases the deployment of networks for parallel computers of different scales, from VLSI systems to the largest supercomputers.
Paper Structure (6 sections, 4 figures, 1 table, 2 algorithms)

This paper contains 6 sections, 4 figures, 1 table, 2 algorithms.

Table of Contents

  1. Introduction
  2. Choice of ports and CIN instances
  3. Minimal Routing
  4. LACIN: Linear Arranged CIN
  5. LACIN for Large-scale Networks
  6. Conclusions

Figures (4)

  • Figure 1: CIN of 8 switches and 64 end-points, with 4 of its 28 links in bold.
  • Figure 2: Port Pairing $P$ Matrices with $N=8$ for (a) anisoport Swap, (b) isoport Circle and (c) isoport XOR CIN instances. $1$-factor $i=3$ in bold.
  • Figure 3: A 2D CIN implementation of size 16 as a hierarchy of CINs of size 4. The links of the outer CIN are bundles, each comprising 16 inner links.
  • Figure 4: Top view of a 4$\times$4$\times$4 HyperX using XOR LACINs. Each rack stacks 4 switches. Only inter-rack connections, grouped into super-ports, are shown.