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Investigation of Hardware Architecture Effects on Quantum Algorithm Performance: A Comparative Hardware Study

Askar Oralkhan, Temirlan Zhaxalykov

TL;DR

This study benchmarks five foundational quantum algorithms across heterogeneous hardware (trapped-ion, superconducting, and simulator backends) using Amazon Braket to quantify how architecture shapes performance. By evaluating Bell, GHZ, QFT, Grover, and QAOA with metrics like fidelity, CHSH violation, success probability, circuit depth, and gate counts, the work reveals strong device-dependent behavior driven by topology and noise. The results show trapped-ion platforms achieving higher fidelities and entanglement quality, while superconducting devices suffer from connectivity-induced depth and gate errors, especially for deeper circuits and variational routines (e.g., QAOA). These findings underscore the need for hardware-aware algorithm selection, co-design of compilation and connectivity mapping, and robust error-mitigation strategies to extend the practical reach of NISQ-era quantum computation.

Abstract

Cloud-accessible quantum processors enable direct execution of quantum algorithms on heterogeneous hardware platforms. Unlike classical systems, however, identical quantum circuits may exhibit substantially different behavior across devices due to architectural variations in qubit connectivity, gate fidelity, and coherence times. In this work, we systematically benchmark five representative quantum algorithms - Bell state preparation, GHZ state generation, Quantum Fourier Transform (QFT), Grover's Search, and the Quantum Approximate Optimization Algorithm (QAOA) - across trapped-ion, superconducting, and simulator backends using Amazon Braket. Performance metrics including fidelity, CHSH violation, success probability, circuit depth, and gate counts are evaluated. Our results demonstrate a strong dependence of algorithmic performance on hardware topology and noise characteristics. For example, 10-qubit GHZ states achieved fidelities above 0.8 on trapped-ion hardware, while superconducting platforms dropped below 0.15 due to routing overhead and accumulated two-qubit gate errors. These findings highlight the importance of hardware-aware algorithm selection and provide practical guidance for benchmarking in the NISQ era.

Investigation of Hardware Architecture Effects on Quantum Algorithm Performance: A Comparative Hardware Study

TL;DR

This study benchmarks five foundational quantum algorithms across heterogeneous hardware (trapped-ion, superconducting, and simulator backends) using Amazon Braket to quantify how architecture shapes performance. By evaluating Bell, GHZ, QFT, Grover, and QAOA with metrics like fidelity, CHSH violation, success probability, circuit depth, and gate counts, the work reveals strong device-dependent behavior driven by topology and noise. The results show trapped-ion platforms achieving higher fidelities and entanglement quality, while superconducting devices suffer from connectivity-induced depth and gate errors, especially for deeper circuits and variational routines (e.g., QAOA). These findings underscore the need for hardware-aware algorithm selection, co-design of compilation and connectivity mapping, and robust error-mitigation strategies to extend the practical reach of NISQ-era quantum computation.

Abstract

Cloud-accessible quantum processors enable direct execution of quantum algorithms on heterogeneous hardware platforms. Unlike classical systems, however, identical quantum circuits may exhibit substantially different behavior across devices due to architectural variations in qubit connectivity, gate fidelity, and coherence times. In this work, we systematically benchmark five representative quantum algorithms - Bell state preparation, GHZ state generation, Quantum Fourier Transform (QFT), Grover's Search, and the Quantum Approximate Optimization Algorithm (QAOA) - across trapped-ion, superconducting, and simulator backends using Amazon Braket. Performance metrics including fidelity, CHSH violation, success probability, circuit depth, and gate counts are evaluated. Our results demonstrate a strong dependence of algorithmic performance on hardware topology and noise characteristics. For example, 10-qubit GHZ states achieved fidelities above 0.8 on trapped-ion hardware, while superconducting platforms dropped below 0.15 due to routing overhead and accumulated two-qubit gate errors. These findings highlight the importance of hardware-aware algorithm selection and provide practical guidance for benchmarking in the NISQ era.
Paper Structure (24 sections, 19 equations, 14 figures, 6 tables)

This paper contains 24 sections, 19 equations, 14 figures, 6 tables.

Table of Contents

  1. Introduction
  2. Methods and Materials
  3. Literature Review
  4. Materials
  5. IonQ Forte and Aria
  6. IQM Garnet
  7. Rigetti Ankaa-3
  8. State Vector Simulator (SV1)
  9. Algorithm Benchmarks
  10. The Bell State
  11. GHZ state
  12. Quantum Fourier Transform (QFT)
  13. Grover’s Search
  14. Quantum Approximate Optimization Algorithm (QAOA)
  15. Methodology
  16. ...and 9 more sections

Figures (14)

  • Figure 1: Quantum circuit used to prepare the Bell state $|\Phi^+\rangle$.
  • Figure 2: Circuit diagram for preparing an $n$-qubit GHZ state.
  • Figure 3: General structure of the $n$-qubit Quantum Fourier Transform (QFT).
  • Figure 4: Grover's algorithm iteration: oracle followed by diffusion operator.
  • Figure 5: Structure of a depth-$p$ Quantum Approximate Optimization Algorithm.
  • ...and 9 more figures