SurgeQ: A Hybrid Framework for Ultra-Fast Quantum Processor Design and Crosstalk-Aware Circuit Execution

TL;DR

SurgeQ tackles the dual challenge of speeding up two-qubit gates and mitigating crosstalk in superconducting quantum processors. It does so via a hardware–software co-design: a design phase that strengthens couplings to realize faster CZ-like gates, and an execution phase that uses a Crosstalk-Free Scheduler guided by a Surge factor $s$ to suppress amplified crosstalk. The framework introduces a Surge Factor Calibration module to identify the optimal $s$ balancing decoherence and crosstalk errors, and a MIS-based scheduler with pattern substitutions to eliminate nearest-neighbor ZZ crosstalk while keeping depth growth manageable. Evaluations across a diverse benchmark suite show SurgeQ generally achieves higher fidelity than contemporary baselines, with fidelity improvements up to $10^6$ in large circuits and robust performance across topologies like heavy-hex and grid. This hybrid design approach advances practical quantum advantage by enabling ultra-fast, high-fidelity circuit execution on near-term superconducting devices, and lays groundwork for scaling to larger systems and integration with fault-tolerant modules.

Abstract

Executing quantum circuits on superconducting platforms requires balancing the trade-off between gate errors and crosstalk. To address this, we introduce SurgeQ, a hardware-software co-design strategy consisting of a design phase and an execution phase, to achieve accelerated circuit execution and improve overall program fidelity. SurgeQ employs coupling-strengthened, faster two-qubit gates while mitigating their increased crosstalk through a tailored scheduling strategy. With detailed consideration of composite noise models, we establish a systematic evaluation pipeline to identify the optimal coupling strength. Evaluations on a comprehensive suite of real-world benchmarks show that SurgeQ generally achieves higher fidelity than up-to-date baselines, and remains effective in combating exponential fidelity decay, achieving up to a million-fold improvement in large-scale circuits.

Figures (4)

• Figure 1: Overview of SurgeQ's strategies on circuit execution. (a) Qubit connectivity graph for the example circuit. (b) Illustration of tunable couplers with adjustable coupling strengths. (c) Execution schedules before (top) and after (bottom) applying SurgeQ. The initial schedule contains multiple simultaneous CZ gates on adjacent qubits, leading to crosstalk events (highlighted with red arrows and yellow lightning markers, corresponding to colored coupling paths in (a)). The SurgeQ-optimized schedule jointly applies gate-level scheduling and coupling-strength tuning to resolve all crosstalk conflicts and significantly reduce execution time.
• Figure 2: Overview of the SurgeQ framework. In addition to the standard workflow of quantum processor design and circuit execution, the Surge Factor Calibration Unit is introduced to evaluate performance gains achieved through highly optimized circuit execution that avoids crosstalk penalties, as indicated by the bi-directional red arrows. The optimal Surge factor guides the selection of appropriate coupling strengths, as shown by the blue arrow.
• Figure 3: (a) Pattern substitution demonstration. The topmost pattern represents the desired form of pattern substitution. The rest patterns illustrate the current set of pattern substitutions available in our library. (b) Example topological layout of the qubits for (c)(d). The nodes in the topological layout represent qubits while edges denote the coupling between qubits. (c)(d) An example of a scheduling algorithm for the quantum circuit (c) with result (d). We omit the rotation angle $\theta$ around the $Z$ axis of $R_z(\theta)$ gate, as the pattern substitution and merging of $R_z(\theta)$ gates involving changes in $\theta$ of certain $R_z(\theta)$ are irrelevant to our approach. The duration of the whole layer is decided by the longest gate inside, with the timing inconsistency compensated by idle time in each layer. The enclosed parts in (c) are identified as structures that can undergo pattern substitution. In the first loop of the algorithm, the two-qubit gate set $\{q_2\text{-}q_3,q_5\text{-}q_6\}$ is the MIS found, while a pattern containing $q_0$-$q_1$, along with their subsequent single-qubit gates, has been identified. The same line of thought is also applied in the following loop.
• Figure 4: (a) Comparison of fidelity across several representative circuit families under different baselines. All circuits are from the dataset described in \ref{['Chap:Benchmarks']}, and n denotes the number of qubits, with QSIH circuits fixed to 2 Trotter steps. Due to XtalkSched's exponential-time complexity and the resulting prohibitive compilation times, results for QSIH with n=30 are unavailable. Overall, SurgeQ achieves higher fidelity than the alternatives in most cases. (b) The Surge Factor Calibration for QSIH circuits. All the data are the ratio compared with the results obtained by using only the base compilation---Qiskit O3. A lower duration ratio and a higher fidelity ratio are indicative of superior performance. Legends such as hhex/grid, dur/fid, and $20$/$100$ indicate the corresponding data points' attributes: topology (heavy hexagon or grid), metric (duration ratio or fidelity ratio), and circuit size ($20$-qubit or $100$-qubit). (c) Benchmarking results of SurgeQ across a comprehensive suite of quantum circuits derived from real-world quantum applications, evaluated in terms of depth, duration, and fidelity ratios, with the Surge factor set to $s=1.8$. (d) Ablation experiment of SurgeQ for QSIH execution on grid backend with $s=1.7$