Implementation of Tensor Network Simulation TN-Sim under NWQ-Sim

TL;DR

The paper tackles the challenge of classically simulating large-scale quantum circuits on HPC resources by implementing TN-Sim as a TAMM-backed backend within NWQ-Sim, bridging local ITensor-based simulations and distributed HPC contractions. It introduces a dual-backend architecture, gate fusion, and a task-based, layer-wise parallelization strategy to efficiently contract wide circuits, while validating scalability on the Perlmutter supercomputer and outlining portability to AMD and Intel HPC systems. Key contributions include the integration of MPS-based quantum circuit simulation with distributed tensor contraction via TAMM, a layered parallelization framework, and demonstrated performance on GHZ and brickwork circuits, highlighting near-linear scaling with qubit count under fixed bond dimensions and the impact of communication overhead. The work advances the practical capacity to benchmark, optimize, and prototype tensor-network algorithms for quantum circuit simulation, circuit cutting, and hardware-aware compilation across diverse HPC architectures.

Abstract

Large-scale tensor network simulations are crucial for developing robust complexity-theoretic bounds on classical quantum simulation, enabling circuit cutting approaches, and optimizing circuit compilation, all of which aid efficient quantum computation on limited quantum resources. Modern exascale high-performance computing platforms offer significant potential for advancing tensor network quantum circuit simulation capabilities. We implement TN-Sim, a tensor network simulator backend within the NWQ-Sim software package that utilizes the Tensor Algebra for Many-body Methods (TAMM) framework to support both distributed HPC-scale computations and local simulations with ITensor. To optimize the scale up in computation across multiple nodes we implement a task based parallelization scheme to demonstrate parallelized gate contraction for wide quantum circuits with many gates per layer. Through the integration of the TAMM framework with Matrix Product State (MPS) tensor network approaches, we deliver a simulation environment that can scale from local systems to HPC clusters. We demonstrate an MPS tensor network simulator running on the state-of-the-art Perlmutter (NVIDIA) supercomputer and discuss the potential portability of this software to HPC clusters such as Frontier (AMD) and Aurora (Intel). We also discuss future improvements including support for different tensor network topologies and enhanced computational efficiency.

Figures (7)

• Figure 1: Depiction of MPS tensor train filled with rank 3 tensors, connected to a graph one and two qubit gates.
• Figure 2: Merging two adjacent MPS site tensors into a single rank-4 tensor in TAMM.
• Figure 3: (a) Layer decomposition of tensor-network quantum gates into non-overlapping qubit layers. (b) Subgroups executing gates in parallel in a non-overlapping qubit layer.
• Figure 4: ITensor TN-Sim backend versus the statevector method used by SV-Sim. Simulation time over circuit width on the tensor network simulator scales near-linearly, while state-vector simulation times grow exponentially.
• Figure 5: Circuit diagram for a brickwork state. Alternating between single and two qubit gates this circuit structure is nearly maximally dense per layer, which can be readily parallelized in our task based parallelism.