A current source with metrological precision made on a 300mm silicon MOS process

TL;DR

This work demonstrates a metrologically precise single-electron current source realized in an industrial-grade 300 mm silicon CMOS process, achieving an inferred error near 0.01 ppm at zero magnetic field. The device is a gate-defined dynamic quantum dot pumped at $f=100$ MHz, with an inferred error of $7.8\times10^{-9}$ supported by the decay cascade model and a charging energy of $E_c\approx8$ meV together with a crossover temperature of $T_0\approx5$ K. The results indicate strong potential for scaling via parallel devices and integration with control electronics, and the authors discuss architectural strategies like shared barrier gates and energy-selective confinement gates to enable high-yield, metrologically accurate current sources and possible closure of the Quantum Metrological Triangle. Overall, the study advances silicon-based quantum current standards toward practical nanoampere-scale metrology and large-scale integration.

Abstract

Although the measurement of current is now defined with respect to the electronic charge, producing a current standard based on a single-electron source remains challenging. The error rate of a source must be below 0.01 ppm, and many such sources must be operated in parallel to provide practically useful values of current in the nanoampere range. Achieving a single electron source using an industrial grade 300 mm wafer silicon metal oxide semiconductor (MOS) process could offer a powerful route for scaling, combined with the ability for integration with control and measurement electronics. Here, we present measurements of such a single-electron source indicating an error rate of 0.008 ppm, below the error threshold to satisfy the SI Ampere, and one of the lowest error rates reported, implemented using a gate-defined quantum dot device fabricated on an industry-grade silicon MOS process. Further evidence supporting the accuracy of the device is obtained by comparing the device performance to established models of quantum tunnelling, which reveal the mechanism of operation of our source at the single particle level. The low error rate observed in this device motivates the development of scaled arrays of parallel sources utilising Si MOS devices to realise a new generation of metrologically accurate current standards.

Figures (7)

• Figure 1: A single-electron pump produced on a Si MOS 300 mm process. (a) Illustration of the device design and electrical connections with expected potential profile beneath. (b) With each cycle of $V_{\rm G1}^{\rm ac}$, charge is (i) loaded into the inter-gate QD; (ii) Sequential back-tunnelling of charge occurs, leaving capture of $n$ charges; (iii) the charge(s) are isolated in the dynamic QD; finally (iv) the charge(s) are ejected to the drain forming the pumped current $I_{p}=nef$. (c) Measured current as a function of dc gate voltages, with $V_{\rm G1}^{\rm ac} \sim 0.8$ V at 100 MHz. Colour scale shows $I_{p}/ef$, denoting the number of charges $n$ pumped per cycle. Contour lines are at unit increment. (d) Current measured as a function of the dc voltage on $V_{\rm G2}$ (dashed line in (c)) with a fit (red) to the decay cascade model (Eq. \ref{['dc fit']}) verifying the sequential tunnelling regime of operation. (ii) Fitting the deviation from single-electron tunnelling, $\left| 1-I_{p}/ef \right|$ indicates an error $<10^{-8}$.
• Figure 2: Plot of the sharpness (accuracy approximator) $\delta_{1}$ (Eq. \ref{['dc fit']}) with sample temperature shows a transition at $T_{0}\sim5$ K from the tunnelling-limited regime to the thermal regime, captured by the fit to Eq. \ref{['g fit']} (blue). From this we derive the properties of the QD-gate system that define the high-accuracy operation. Error bars are systematic from fit to Eq. \ref{['dc fit']}.
• Figure 3: (a) 2D map, analogous to Fig. 1(c), but at $V_{\rm TG} = 1.1$ V, shows clear presence of additional bounding line (ii), contrary to the only expected loading bound (i). (b) The vertex between the split loading lines – the balance point $P$ - is seen to vary in $V_{\rm G2}$ with $V_{\rm C2}$ but not $V_{\rm C1}$. (c) We derive the balance point $P$ as the point at which the ejection tunnel barrier height aligns with the QD energy at the time of maximum potential (stage (iv) in Fig. \ref{['fig:fig1']}(c), towards the maximum value of $V_{\rm G1}^{\rm ac}$). For lower barriers, case (i), ejection can occur across the G2 span. For higher barriers, case (ii), ejection only happens in the pinned state for values $V_{\rm G1} >$ case (i).
• Figure S1: Pump maps with varying $V_{\rm TG}$. Contours mark successive electrons pumped per cycle. The breakdown in the single electron tunnelling regime is seen with increasing $V_{\rm TG}$.
• Figure S2: Accuracy evaluation under the effect of the C gates. (a) the sharpness $\delta_{1}$ from the fits with varying C-gate voltage shows no trend. (b) data with a fit to eqn. \ref{['dc fit']}.