Low-Complexity Planar Beyond-Diagonal RIS Architecture Design Using Graph Theory
Matteo Nerini, Zheyu Wu, Shanpu Shen, Bruno Clerckx
TL;DR
This work shows how graph theory can identify BD-RIS architectures that can be realized on a double-layer PCB, introducing planar-connected RIS and maximal-planar-connected RIS as the most flexible yet practically implementable designs under planar constraints. It provides necessary planarity conditions, analyzes existing BD-RIS architectures for planarity, and presents three maximal-planar-connected examples achieving high degrees of freedom with 4N−6 interconnections, while preserving planarity. Through joint precoding and RIS optimization, the paper demonstrates a trade-off between sum-rate performance and circuit complexity, revealing that maximal-planar-connected RIS offers a favorable balance for practical deployment. The results offer concrete design guidelines for low-complexity BD-RIS architectures capable of nearing fully-connected performance in multi-user scenarios.
Abstract
Reconfigurable intelligent surfaces (RISs) enable programmable control of the wireless propagation environment and are key enablers for future networks. Beyond-diagonal RIS (BD-RIS) architectures enhance conventional RIS by interconnecting elements through tunable impedance components, offering greater flexibility with higher circuit complexity. However, excessive interconnections between BD-RIS elements require multi-layer printed circuit board (PCB) designs, increasing fabrication difficulty. In this letter, we use graph theory to characterize the BD-RIS architectures that can be realized on double-layer PCBs, denoted as planar-connected RISs. Among the possible planar-connected RISs, we identify the ones with the most degrees of freedom, expected to achieve the best performance under practical constraints.
