Lightweight Transformer Architectures for Edge Devices in Real-Time Applications
Hema Hariharan Samson
TL;DR
This work surveys lightweight transformer architectures and optimization strategies for edge devices, addressing the core challenge of enabling real-time AI under strict resource constraints by leveraging distillation, pruning, quantization, and hardware-aware design. It catalogues architecture families (e.g., MobileBERT, TinyBERT, DistilBERT, EfficientFormer, EdgeFormer, MobileViT) and efficient attention mechanisms, then several industry-standard tooling and platforms to realize on-device inference. The analysis presents strong empirical evidence that 75–96% of full-model accuracy is achievable with 4–10× model size reduction and 3–9× latency reductions, often on devices consuming 2–5 W, with memory bandwidth often dictating throughput. Key findings highlight memory–latency tradeoffs, quantization sweet spots, and the superior gains from two-stage distillation and hardware-aware NAS, providing a practical deployment pipeline that yields 8–12× size reduction with less than 2% accuracy loss. The results inform practical guidance for practitioners and outline future directions in long-context processing, multimodal edge AI, and automated compression pipelines.
Abstract
The deployment of transformer-based models on resource-constrained edge devices represents a critical challenge in enabling real-time artificial intelligence applications. This comprehensive survey examines lightweight transformer architectures specifically designed for edge deployment, analyzing recent advances in model compression, quantization, pruning, and knowledge distillation techniques. We systematically review prominent lightweight variants including MobileBERT, TinyBERT, DistilBERT, EfficientFormer, EdgeFormer, and MobileViT, providing detailed performance benchmarks on standard datasets such as GLUE, SQuAD, ImageNet-1K, and COCO. Our analysis encompasses current industry adoption patterns across major hardware platforms (NVIDIA Jetson, Qualcomm Snapdragon, Apple Neural Engine, ARM architectures), deployment frameworks (TensorFlow Lite, ONNX Runtime, PyTorch Mobile, CoreML), and optimization strategies. Experimental results demonstrate that modern lightweight transformers can achieve 75-96% of full-model accuracy while reducing model size by 4-10x and inference latency by 3-9x, enabling deployment on devices with as little as 2-5W power consumption. We identify sparse attention mechanisms, mixed-precision quantization (INT8/FP16), and hardware-aware neural architecture search as the most effective optimization strategies. Novel findings include memory-bandwidth bottleneck analysis revealing 15-40M parameter models achieve optimal hardware utilization (60-75% efficiency), quantization sweet spots for different model types, and comprehensive energy efficiency profiling across edge platforms. We establish real-time performance boundaries and provide a practical 6-step deployment pipeline achieving 8-12x size reduction with less than 2% accuracy degradation.
