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Gradient descent reliably finds depth- and gate-optimal circuits for generic unitaries

Janani Gomathi, Alex Meiburg

TL;DR

This work shows that gradient-descent optimization can reliably produce depth- and gate-optimal circuits for generic $n$-qubit unitaries, provided the circuit skeleton has enough parameter degrees of freedom. By fixing a topology and accelerating local updates with an SVD-based step, the method achieves convergence across 2-, 4-, and 6-qubit systems and remains effective under connectivity constraints. The authors derive a parameter-counting bound guiding the required number of layers and demonstrate that underparameterized topologies lead to stagnation, while adequately parameterized designs converge to optimal circuits with minimal CNOTs and total gates. The approach offers a practical, parameter-efficient alternative to brute-force synthesis or generic compilers, with strong implications for hardware-constrained quantum circuit design.

Abstract

When the gate set has continuous parameters, synthesizing a unitary operator as a quantum circuit is always possible using exact methods, but finding minimal circuits efficiently remains a challenging problem. The landscape is very different for compiled unitaries, which arise from programming and typically have short circuits, as compared with generic unitaries, which use all parameters and typically require circuits of maximal size. We show that simple gradient descent reliably finds depth- and gate-optimal circuits for generic unitaries, including in the presence of restricted chip connectivity. This runs counter to earlier evidence that optimal synthesis required combinatorial search, and we show that this discrepancy can be explained by avoiding the random selection of certain parameter-deficient circuit skeletons.

Gradient descent reliably finds depth- and gate-optimal circuits for generic unitaries

TL;DR

This work shows that gradient-descent optimization can reliably produce depth- and gate-optimal circuits for generic -qubit unitaries, provided the circuit skeleton has enough parameter degrees of freedom. By fixing a topology and accelerating local updates with an SVD-based step, the method achieves convergence across 2-, 4-, and 6-qubit systems and remains effective under connectivity constraints. The authors derive a parameter-counting bound guiding the required number of layers and demonstrate that underparameterized topologies lead to stagnation, while adequately parameterized designs converge to optimal circuits with minimal CNOTs and total gates. The approach offers a practical, parameter-efficient alternative to brute-force synthesis or generic compilers, with strong implications for hardware-constrained quantum circuit design.

Abstract

When the gate set has continuous parameters, synthesizing a unitary operator as a quantum circuit is always possible using exact methods, but finding minimal circuits efficiently remains a challenging problem. The landscape is very different for compiled unitaries, which arise from programming and typically have short circuits, as compared with generic unitaries, which use all parameters and typically require circuits of maximal size. We show that simple gradient descent reliably finds depth- and gate-optimal circuits for generic unitaries, including in the presence of restricted chip connectivity. This runs counter to earlier evidence that optimal synthesis required combinatorial search, and we show that this discrepancy can be explained by avoiding the random selection of certain parameter-deficient circuit skeletons.
Paper Structure (22 sections, 7 equations, 17 figures)

This paper contains 22 sections, 7 equations, 17 figures.

Table of Contents

  1. Introduction
  2. Background
  3. Problem Setup and Method
  4. Parametrization
  5. Cost Function
  6. Approximation to the closest unitary through SVD
  7. Layer Calculation
  8. Results
  9. Circuit decomposition and choice of topology
  10. Numerics
  11. Handling Connectivity Constraints
  12. Conclusion
  13. Acknowledgements
  14. Reliable convergence of 4-qubit and 6-qubit systems
  15. 4-qubit system
  16. ...and 7 more sections

Figures (17)

  • Figure 1: Circuit decompositions for 2-, 4-, and 6-qubit unitaries.
  • Figure 2: Comparison of convergence behavior for different initializations (left) and different target unitaries (right).
  • Figure 3: Convergences of five random $16 \times 16$ target unitaries optimized through the gradient-based algorithm for $\ell=32$. The y-axis is in log scale.
  • Figure 4: Convergences of the same $16 \times 16$ target unitary initialized with five different sets of parameters for $\ell=32$. The y-axis is in log scale.
  • Figure 5: Convergences of five random $64 \times 64$ target unitaries optimized through the gradient-based algorithm for $\ell=341$.The y-axis is in log scale.
  • ...and 12 more figures