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Minimization of AND-XOR Expressions with Decoders for Quantum Circuits

Sonia Yang, Ali Al-Bayaty, Marek Perkowski

TL;DR

This work introduces multi-valued input, binary output (MVI) logic as a foundation for reversible quantum circuit synthesis, formulating two canonical forms—MVI-FPRM and MVI-GRM—to minimize quantum costs. It develops two practical synthesis paths: (i) a products-matching method to compute exact MVI-FPRM representations and corresponding decoder-based circuits, and (ii) a butterfly-diagram approach to transform minterms into fixed polarities; MVI-GRM further factorizes MVI-FPRM forms to reduce circuit size. Through detailed examples including a 2-bit adder and multi-output functions, the paper demonstrates substantial cost benefits over ESOP-based realizations, particularly as circuit size grows and decoder costs amortize. The results establish a concrete, decoder-enabled framework for low-cost quantum circuit synthesis, with future work focusing on decoder selection, variable pairing, and extending to incompletely specified functions.

Abstract

This paper introduces a new logic structure for reversible quantum circuit synthesis. Our synthesis method aims to minimize the quantum cost of reversible quantum circuits with decoders. In this method, multi-valued input, binary output (MVI) functions are utilized as a mathematical concept only, but the circuits are binary. We introduce the new concept of ``Multi-Valued Input Fixed Polarity Reed-Muller (MVI-RM)" forms. Our decoder-based circuit uses three logical levels in contrast to commonly-used methods based on Exclusive-or Sum of Products (ESOP) with two levels (AND-XOR expressions), realized by Toffoli gates. In general, the high number of input qubits in the resulting Toffoli gates is a problem that greatly impacts the quantum cost. Using decoders decreases the number of input qubits in these Toffoli gates. We present two practical algorithms for three-level circuit synthesis by finding the MVI-FPRM: products-matching and the newly developed butterfly diagrams. The best MVI-FPRM forms are factorized and reduced to approximate Multi-Valued Input Generalized Reed-Muller (MVI-GRM) forms.

Minimization of AND-XOR Expressions with Decoders for Quantum Circuits

TL;DR

This work introduces multi-valued input, binary output (MVI) logic as a foundation for reversible quantum circuit synthesis, formulating two canonical forms—MVI-FPRM and MVI-GRM—to minimize quantum costs. It develops two practical synthesis paths: (i) a products-matching method to compute exact MVI-FPRM representations and corresponding decoder-based circuits, and (ii) a butterfly-diagram approach to transform minterms into fixed polarities; MVI-GRM further factorizes MVI-FPRM forms to reduce circuit size. Through detailed examples including a 2-bit adder and multi-output functions, the paper demonstrates substantial cost benefits over ESOP-based realizations, particularly as circuit size grows and decoder costs amortize. The results establish a concrete, decoder-enabled framework for low-cost quantum circuit synthesis, with future work focusing on decoder selection, variable pairing, and extending to incompletely specified functions.

Abstract

This paper introduces a new logic structure for reversible quantum circuit synthesis. Our synthesis method aims to minimize the quantum cost of reversible quantum circuits with decoders. In this method, multi-valued input, binary output (MVI) functions are utilized as a mathematical concept only, but the circuits are binary. We introduce the new concept of ``Multi-Valued Input Fixed Polarity Reed-Muller (MVI-RM)" forms. Our decoder-based circuit uses three logical levels in contrast to commonly-used methods based on Exclusive-or Sum of Products (ESOP) with two levels (AND-XOR expressions), realized by Toffoli gates. In general, the high number of input qubits in the resulting Toffoli gates is a problem that greatly impacts the quantum cost. Using decoders decreases the number of input qubits in these Toffoli gates. We present two practical algorithms for three-level circuit synthesis by finding the MVI-FPRM: products-matching and the newly developed butterfly diagrams. The best MVI-FPRM forms are factorized and reduced to approximate Multi-Valued Input Generalized Reed-Muller (MVI-GRM) forms.
Paper Structure (24 sections, 2 theorems, 65 equations, 33 figures, 23 tables)

This paper contains 24 sections, 2 theorems, 65 equations, 33 figures, 23 tables.

Table of Contents

  1. Introduction
  2. Background
  3. Binary Reed-Muller Forms
  4. Boolean Expansions
  5. Reversible Quantum Gates
  6. Quantum Costs
  7. ESOP versus GRM and Factorization
  8. Butterfly Diagrams
  9. Multi-Valued Input, Binary Output Functions
  10. Operating with Multi-Valued Input Literals
  11. Decoders
  12. Polarity With Multi-Valued Input Literals
  13. Ternary Input Shannon and Davio-like Expansions
  14. Extending Reed-Muller Forms to Multi-Valued Input Functions
  15. Circuit Synthesis Based on MVI-FPRM
  16. ...and 9 more sections

Key Result

Theorem 1

A multi-valued literal $X^S$, where $S \subseteq V=\{0,1,\dots,v-1\}$, can be represented by $v$ polarity literals $P^1, P^2, \dots, P^v$. The values of the polarity literals form the row vectors $T^r$ of the linearly independent $v \times v$ matrix $P$.

Figures (33)

  • Figure 1: Reversible quantum gates.
  • Figure 2: Reversible quantum circuit realizations of $f$ from Example \ref{['ex:esop-vs-grm']}.
  • Figure 3: Karnaugh map of $f$ showing the groups for the GRM form: $\textcolor{orange}{x_1x_2} \oplus \textcolor{red}{\bar{x}_1\bar{x}_3} \oplus \textcolor{blue}{x_2\bar{x}_3}$.
  • Figure 4: The butterfly diagram kernels for the binary Shannon, positive Davio, and negative Davio expansions.
  • Figure 5: The butterfly diagram that transforms a function of $x_1$ and $x_2$ from the XOR of minterms: $\textcolor{mediumblue}{\bar{x}_1\bar{x}_2 \oplus x_1\bar{x}_2 \oplus x_1x_2}$, to the FPRM form with polarity 01: $\textcolor{mediumblue}{\bar{x}_1x_2 \oplus 1}$.
  • ...and 28 more figures

Theorems & Definitions (28)

  • Definition 1
  • Definition 2
  • Definition 3
  • Example 1
  • Definition 4
  • Definition 5
  • Example 2
  • Example 3
  • Definition 6
  • Theorem 1
  • ...and 18 more