Developments in superconducting erasure qubits for hardware-efficient quantum error correction

TL;DR

The paper addresses the scalability challenge of quantum error correction on superconducting hardware by advocating erasure qubits, which convert dominant amplitude-damping errors into heralded, detectable erasures with known locations. It surveys the theory, simulations, and experimental demonstrations showing that erasure errors can dramatically raise fault-tolerance thresholds and improve logical-error scaling when combined with outer codes such as surface codes or LDPC codes. The authors detail three superconducting erasure-qubit implementations (coupled transmons, multimode dimon qubits, and cavity QED) and emphasize near-term benefits for error detection and mitigation, including postselection, as well as the potential for early fault-tolerance. They outline open questions—such as optimal hardware-code co-design, decoding tooling, and effective noise modeling—and advocate for erasure-aware decoding as a crucial step toward scalable, low-overhead quantum computation on near-term devices and beyond.

Abstract

Quantum computers are inherently noisy, and a crucial challenge for achieving large-scale, fault-tolerant quantum computing is to implement quantum error correction. A promising direction that has made rapid recent progress is to design hardware that has a specific noise profile, leading to a significantly higher threshold for noise with certain quantum error correcting codes. This Perspective focuses on erasure qubits, which enable hardware-efficient quantum error correction, by concatenating an inner code built-in to the hardware with an outer code. We focus on implementations of dual-rail encoded erasure qubits using superconducting qubits, giving an overview of recent developments in theory and simulation, and hardware demonstrators. We also discuss the differences between implementations; near-term applications using quantum error detection; and the open problems for developing this approach towards early fault-tolerant quantum computers.

Figures (5)

• Figure 1: A visualisation of the quantum error correction process, which involves encoding data from physical qubits; frequent measurements for errors, decoding, and correction, while applying logical operators to the encoded information; and finally logical measurement to reveal the computational information.
• Figure 2: A visualisation of dual-rail encoding, with arrows indicating the suppressed transitions between states in the logical subspace, and dominant transitions to the ground state (a detectable erasure error).
• Figure 3: Syndrome extraction circuit for a $d=2$ surface code with integrated erasure checks. The data qubits $d_i$ and ancilla $a_Z$ are dual-rail encoded qubits. Each erasure check flags leakage out of the computational subspace, after which the affected qubit is reset before continuing the circuit.
• Figure 4: Comparison of leakage, Pauli, and erasure errors in a minimal surface-code layout, with data qubits $d_i$, ancilla qubits $a_i$, and effective code distance d. Leakage errors escape the computational subspace without any flag (undetectable, distance $d=1$); Pauli errors stay within the subspace and flip stabilisers (detectable, $d=2$); erasure errors initially escape the computational subspace, then are flagged by erasure checks and can be reset and corrected (correctable, $d=3$).
• Figure 5: Three example implementations of superconducting erasure qubits: a) coaxial dimon; b) cavity QED; c) coupled transmons. Panels b) and c) are reproduced from teoh2023dual, figure 4, and huang2025logical, figure 1b, respectively; see the original works for further details.