Design and Quantitative Evaluation of an Embedded EEG Instrumentation Platform for Real-Time SSVEP Decoding

TL;DR

The proposed system is positioned as a quantitatively characterized embedded EEG measurement and processing platform for real-time SSVEP decoding based on an ESP32-S3 microcontroller and an ADS1299 analog front end.

Abstract

This paper presents an embedded EEG instrumentation platform for real-time steady-state visually evoked potential (SSVEP) decoding based on an ESP32-S3 microcontroller and an ADS1299 analog front end. The system performs $8$-channel EEG acquisition, zero-phase bandpass filtering, and canonical correlation analysis entirely on-device, while supporting wireless communication and closed-loop operation without external computation. A central contribution is the quantitative characterization of the platform's measurement integrity. Reported results demonstrate a stable shorted-input noise floor ($\approx 0.08~μ\text{V}_{\text{RMS}}$), tightly bounded sampling jitter ($0.56~μ\text{s}$ standard deviation), and negligible long-term drift ($< 1~\text{ppm}$). Numerical fidelity analysis shows $100\%$ decision agreement between the mixed-precision embedded pipeline and a $64$-bit double-precision reference. Effective common-mode attenuation exceeded $112~\text{dB}$ under balanced conditions, with a localized $26.9~\text{dB}$ degradation observed under source-impedance mismatch. Closed-loop validation achieved $99.17\%$ online accuracy and an information transfer rate of $27.66~\text{bits/min}$. These results position the proposed system as a quantitatively characterized embedded EEG measurement and processing platform for real-time SSVEP decoding.

Figures (7)

• Figure 1: Overall architecture of the embedded EEG instrumentation platform. The system integrates battery-powered operation, an ADS1299-based analog front end, an ESP32-S3 microcontroller for on-device zero-phase filtering and CCA-based SSVEP decoding, and a lightweight TCP interface for external communication.
• Figure 2: Embedded firmware architecture. A hardware-driven ADS1299 DRDY interrupt service routine triggers the Core 0 data acquisition task. Core 0 performs epoch extraction, zero-phase bandpass filtering, and CCA-based classification only when the trial state is enabled through the phone communication path on Core 1. Core 1 also manages EEG streaming and optional logging. The decision output is returned through the communication task for real-time feedback display on the phone. The timestamp points $t_0$, $t_1$, and $t_2$ denote the onset of filtering, the start of CCA classification, and the completion of the decision output, respectively.
• Figure 3: Measurement setups used for noise characterization and effective common-mode rejection evaluation.
• Figure 4: Closed-loop SSVEP validation setup and operation flow.
• Figure 5: Cumulative distribution of inter-sample intervals measured from ADS1299 DRDY timestamps under OFF and ON operating modes. The dotted vertical line indicates the nominal 2000 $\mu$s sampling period at 500 SPS.