Two-Qubit Module Based on Phonon-Coupled Ge Hole-Spin Qubits: Design, Fabrication, and Readout at 1-4 K

TL;DR

The paper presents a concrete, fabrication-ready two-qubit module that uses phonon-coupled Ge hole-spin qubits operating at $1$--$4~\mathrm{K}$. It combines gate-defined double quantum dots in a strained Ge quantum well with a GHz-scale phononic-crystal cavity suspended in a Ge membrane to mediate a phonon bus for entangling operations, while detailing a compatible nanofabrication flow, materials stack, and RF-readout architecture. Key figures of merit include $g_{sp}/2\pi$ in the $5$--$10$~MHz range, dispersive two-qubit coupling $g_{qq}/2\pi$ in the $0.25$--$1$~MHz range, $T_1$ on the order of $1$~ms within the bandgap, and single-shot readout fidelities $>95\%$ within a few microseconds. The work provides a clear experimental roadmap toward phonon-mediated entangling gates and phonon-enabled sensing, while outlining extensions to larger arrays and hybrid spin–phonon–photon architectures for scalable Ge-based quantum technologies.

Abstract

We present a device-level design for a two-qubit module based on phonon-coupled germanium (Ge) hole-spin qubits operating at $1$-$4~\mathrm{K}$. Building on prior work on phonon-engineered Ge qubits and phononic-crystal (PnC) cavities, we specify a lithography-ready layout that integrates two gate-defined hole-spin qubits in a strained Ge quantum well with a GHz PnC defect mode that mediates a coherent phonon-based interaction. We detail the SiGe/Ge heterostructure, PnC cavity design, and a compatible nanofabrication process flow, including the gate stack, membrane patterning and release, and RF/DC wiring. We further develop a readout architecture combining spin-to-charge conversion with RF reflectometry on a proximal charge sensor, supported by a cryogenic RF chain optimized for operation at $1$-$4~\mathrm{K}$. Finally, we outline the cryogenic measurement environment, tuning procedures, and a stepwise benchmarking program targeting single-qubit control, phonon-bandgap suppression of relaxation channels, and resolvable phonon-mediated two-qubit coupling. The resulting module provides a scalable template for medium-range coupling of Ge hole-spin qubits and connects materials and phonon engineering with circuit-level readout, enabling future experimental demonstrations of entangling gates, Bell-state generation, and phonon-enabled quantum sensing.

Figures (7)

• Figure 1: Conceptual cross-sectional layout of the Ge-based two-qubit module integrated with a PnC cavity. Metal top gates (plunger gates PG$_1$, PG$_2$ and barrier gate BG) are patterned above a dielectric stack and a compressively strained Ge quantum well. Gate-induced depletion in the Ge layer defines two laterally separated hole quantum dots, QD$_1$ and QD$_2$, with center-to-center spacing of $\sim 50~\mathrm{nm}$. The dots reside in a suspended membrane region patterned as a PnC cavity beneath the Ge layer; its engineered acoustic bandgap and localized defect modes spectrally and spatially filter lattice vibrations, enabling controlled phonon-mediated interactions while suppressing leakage into bulk substrate phonons.
• Figure 2: Illustrative SiGe/Ge heterostructure and materials stack for the PnC-integrated two-qubit device. Right: cross-sectional view of the epitaxial stack, comprising a Si substrate, a graded Si$_{1-y}$Ge$_y$ buffer that relaxes the lattice, a relaxed Si$_{1-x}$Ge$_x$ layer that sets the in-plane lattice constant, a compressively strained Ge quantum well hosting the 2DHG, and a SiGe cap, followed by an ALD high-$\kappa$ dielectric and surface passivation layer. Left: a suspended PnC membrane patterned from the same SiGe/Ge stack, hosting the gate-defined quantum dots and the defect cavity.
• Figure 3: Illustrative nanofabrication process flow for the Ge-based two-qubit device. (a) Starting SiGe/Ge heterostructure (Sec. \ref{['sec:heter']}) with definition of mesas and ohmic contacts. (b) Surface preparation, ALD gate dielectric deposition, and patterning of fine metal gates defining the quantum dots and reservoirs. (c) Second aligned lithography and etching steps to form the PnC lattice and defect cavity, followed by selective under-etching to release the suspended membrane. (d) Deposition and patterning of RF coplanar waveguides (CPWs), DC wiring, and bond pads, completing the two-qubit module for packaging and cryogenic measurement.
• Figure 4: Illustrative readout architecture and signal chain. (a) Double-dot qubit pair (QD$_1$, QD$_2$) coupled capacitively to a nearby charge sensor (sensor QD or QPC). Spin-to-charge conversion is performed either by energy-selective tunneling to a reservoir or via Pauli spin blockade between the two dots. (b) The charge sensor is embedded in an RF resonant circuit (LC or CPW resonator) and probed by reflectometry. The input line includes distributed attenuators for thermalization, while the output line passes through a cryogenic low-noise amplifier (LNA) before further amplification, down-conversion, and digitization at room temperature. Multiple resonators can be frequency multiplexed on a single RF line in future multi-qubit devices.
• Figure 5: Illustrative cryogenic measurement setup for the Ge-based two-qubit device. The chip is wire-bonded to a PCB or ceramic carrier mounted on the cold stage of a $1$--$4~\mathrm{K}$ cryostat inside a superconducting magnet. DC gate and bias lines (left) pass through room-temperature low-pass filters, cryogenic RC or powder filters, and thermal anchoring stages before reaching the chip. RF lines for EDSR and reflectometry (right) are routed through distributed attenuators and filters on the input side and through a cryogenic low-noise amplifier (LNA) and additional stages on the output side. Thermometers and heaters on the sample stage provide temperature control and stabilization over the $1$--$4~\mathrm{K}$ range.