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Image Synthesis Using Spintronic Deep Convolutional Generative Adversarial Network

Saumya Gupta, Abhinandan, Venkatesh vadde, Bhaskaran Muralidharan, Abhishek Sharma

TL;DR

The paper tackles the high energy cost of generative adversarial networks by proposing a full end-to-end spintronic CMOS-spintronic DCGAN. It introduces a 6-bit skyrmion synapse for in-memory convolutional weights and domain-wall based ReLU and Leaky ReLU activations, with a generator upsampling implemented as zero-padded convolution. The approach is validated on Fashion-MNIST and Anime Face, achieving Fréchet Inception Distances of 27.5 and 45.4 respectively, while demonstrating low forward/weight-update energy and end-to-end training compatibility. This hardware-aware DCGAN demonstrates the feasibility and potential of energy-efficient, spintronic-accelerated generative models for edge and real-time applications.

Abstract

The computational requirements of generative adversarial networks (GANs) exceed the limit of conventional Von Neumann architectures, necessitating energy efficient alternatives such as neuromorphic spintronics. This work presents a hybrid CMOS-spintronic deep convolutional generative adversarial network (DCGAN) architecture for synthetic image generation. The proposed generative vision model approach follows the standard framework, leveraging generator and discriminators adversarial training with our designed spintronics hardware for deconvolution, convolution, and activation layers of the DCGAN architecture. To enable hardware aware spintronic implementation, the generator's deconvolution layers are restructured as zero padded convolution, allowing seamless integration with a 6-bit skyrmion based synapse in a crossbar, without compromising training performance. Nonlinear activation functions are implemented using a hybrid CMOS domain wall based Rectified linear unit (ReLU) and Leaky ReLU units. Our proposed tunable Leaky ReLU employs domain wall position coded, continuous resistance states and a piecewise uniaxial parabolic anisotropy profile with a parallel MTJ readout, exhibiting energy consumption of 0.192 pJ. Our spintronic DCGAN model demonstrates adaptability across both grayscale and colored datasets, achieving Fr'echet Inception Distances (FID) of 27.5 for the Fashion MNIST and 45.4 for Anime Face datasets, with testing energy (training energy) of 4.9 nJ (14.97~nJ/image) and 24.72 nJ (74.7 nJ/image).

Image Synthesis Using Spintronic Deep Convolutional Generative Adversarial Network

TL;DR

The paper tackles the high energy cost of generative adversarial networks by proposing a full end-to-end spintronic CMOS-spintronic DCGAN. It introduces a 6-bit skyrmion synapse for in-memory convolutional weights and domain-wall based ReLU and Leaky ReLU activations, with a generator upsampling implemented as zero-padded convolution. The approach is validated on Fashion-MNIST and Anime Face, achieving Fréchet Inception Distances of 27.5 and 45.4 respectively, while demonstrating low forward/weight-update energy and end-to-end training compatibility. This hardware-aware DCGAN demonstrates the feasibility and potential of energy-efficient, spintronic-accelerated generative models for edge and real-time applications.

Abstract

The computational requirements of generative adversarial networks (GANs) exceed the limit of conventional Von Neumann architectures, necessitating energy efficient alternatives such as neuromorphic spintronics. This work presents a hybrid CMOS-spintronic deep convolutional generative adversarial network (DCGAN) architecture for synthetic image generation. The proposed generative vision model approach follows the standard framework, leveraging generator and discriminators adversarial training with our designed spintronics hardware for deconvolution, convolution, and activation layers of the DCGAN architecture. To enable hardware aware spintronic implementation, the generator's deconvolution layers are restructured as zero padded convolution, allowing seamless integration with a 6-bit skyrmion based synapse in a crossbar, without compromising training performance. Nonlinear activation functions are implemented using a hybrid CMOS domain wall based Rectified linear unit (ReLU) and Leaky ReLU units. Our proposed tunable Leaky ReLU employs domain wall position coded, continuous resistance states and a piecewise uniaxial parabolic anisotropy profile with a parallel MTJ readout, exhibiting energy consumption of 0.192 pJ. Our spintronic DCGAN model demonstrates adaptability across both grayscale and colored datasets, achieving Fr'echet Inception Distances (FID) of 27.5 for the Fashion MNIST and 45.4 for Anime Face datasets, with testing energy (training energy) of 4.9 nJ (14.97~nJ/image) and 24.72 nJ (74.7 nJ/image).
Paper Structure (23 sections, 1 equation, 4 figures, 1 table)

This paper contains 23 sections, 1 equation, 4 figures, 1 table.

Table of Contents

  1. Introduction
  2. DCGAN Implementation
  3. Principle of DCGAN
  4. Modified Generator
  5. Spintronic devices for DCGAN
  6. Skyrmion based synapse
  7. CMOS hybrid domain wall ReLU and Leaky ReLU
  8. Proposed methodology
  9. Datasets
  10. Fashion-MNIST dataset
  11. Anime dataset
  12. Network Architecture
  13. Synapse
  14. CMOS hybrid domain wall
  15. ReLU
  16. ...and 8 more sections

Figures (4)

  • Figure 1: (a) Block Diagram of Generative Adversarial Network (b) DCGAN generator block diagram (c) Modified DCGAN generator (d) Deconvolution done with zero padding plus convolution (e) DCGAN discriminator block diagram.
  • Figure 2: (a) 3D schematic of the 6-bit skyrmion synapse device. (b) Biological neural analogy. (c) Skyrmion forces under applied current density. (d) 2D view : FM layer with 64 skyrmions and labyrinthine uniaxial anisotropy profile with outer and inner rings that form the pre synapse region (magnetization direction: blue = into the plane, white = in-plane and red = out of the plane). (e) 2D domain wall track with detector and 3D CMOS domain wall ReLU circuit. (f) 2D domain wall track with left detector (MTJLeft) and right detector (MTJRight),and 3D CMOS domain wall Leaky ReLU circuit. (g) Parabolic uniaxial anisotropy (Ku) profile for ReLU. (h) Normalized conductance versus input charge current with domain wall snapshots for ReLU. (i) Piecewise parabolic uniaxial anisotropy (Ku) profile (PMA) for leaky ReLU device. (j) Normalized conductance versus input charge current with domain wall snapshots for Leaky ReLU.
  • Figure 3: (a) Simulation flow for Skyrmion based synapse. (b) Synaptic weight versus simulation time. (c) Simulation flow for ReLU and Leaky ReLU. (d) ReLU function. (e) Leaky ReLU function realized using a hybrid CMOS domain wall device. (a,e,f) Overall simulation methodology.
  • Figure 4: Generated adversarial image samples for (a) Fashion MNIST dataset (b) Anime face dataset. (c) Generator and Discriminator losses per epoch for (c) Fashion MNIST dataset (d) Anime face dataset.